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长鑫存储2.5D封装设计工程师 I 2.5D Package design Engineer(J13468)

社招全职研发技术类地点:上海状态:招聘

任职要求


1. Strong oral and written communication skills in English
2. CAD skills experienced with formal package drawings 
3. Knowledge of package substrate technology with cored/coreless multiple layers
4. Knowledge of package wafer level package technology with multiple RDL layers
5. Knowledge of advanced and general package process assembly
6. Knowledge of 2.1/2.3/2.5/3D package structure even included conventional package
7. Allegro package design tool such as APD & SiP skill
8. Sigrity XtractIM, PowerSI, Ansys HFSS modeling skill, and ADS SIPI circuit skill
9. Generation package design rule experienced with co-worked adjacent team
10. Have good communication and teamwork skills with calm office manner
11. Generate advanced package design intellectual property of daisy chain and function package product excluded with copycat
12. Fastest turn-around time of design working to meet package product line up
13. Approaching activity with 5Whys question against problem
14. Define/Measure/Analyze/Improve/Control DMAIC mind

工作职责


1. Responsible for design floor plan and bump layout of customer SoC and Silicon/Glass/RDL interposer, and escaping trace line to satisfy SerDes trace line for Signal Integrity and Power Integrity against customer's requirement.
2. Responsible for design of daisy chain to satisfy its design of experiment for advanced 2.5D package structure, cost and warpage specification.
3. Responsible for electrical pre-simulation analysis working with off-chip level of package based on RLC and S-parameter extracted how to optimize SoC SerDes with FCBGA and Silicon/Glass/RDL interposer level.
4. Leading design work of DFM (Design For Manufacturing), DFR (Design For Reliability), and DFP (Design For Performance) with adjacent team and variant vendors.
5. Preparation/discussion/confirmation for unit drawing spec with variants carrier, bonding spec, and package of drawing with adjacent team and variant vendors.
6. Understanding result of signal integrity and power integrity from customer and external department, planning and doing DoE to satisfy with package design activity based on co-worked with adjacent team and variant vendors.
包括英文材料
Assembly+
Allegro+
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