网易高级/资深/专家玩法策划（归唐）
任职要求
1、热爱电影化叙事驱动的3A游戏，对这类游戏的设计理念有深入的研究； 2、对游戏开发充满热情，能长期跟踪了解最新最热的开发理念和技术； 3、对游戏体验有…
工作职责
1、围绕游戏所需要的体验设计相关机制，并跟踪保证以最高的品质实现落地； 2、与关卡、叙事、实现部门的团队成员合作，配合设计效果的迭代与调优； 3、体验和感受各个原型和开发中版本的游戏效果，给出反馈意见和优化方案； 4、配合关卡和工具团队，将实现机制所需流程方法优化，解释清晰； 5、撰写清晰准确的文档，帮助重要设计的交流和存档； 6、协助其他开发部门进行有效沟通，不断提高游戏体验的品质。
1、fintech技术风险能力建设，包含应急能力、变更防御、红蓝攻防、性能容量、资金安全，构建Fintech技术风险体系； 2、参与重大项目的技术风险保障工作，对技术风险领域进行评审和分析； 3、贴身业务，挖掘业务风险，沉淀技术风险领域标杆，释放研发技术风险投入，更聚焦在业务研发上； 4、明星业务，多底盘充满了挑战和机遇，欢迎来战；
The candidate will be the major interface to the optical IO analog/mixed signal design team or vendor. As a member of the analog team, you’ll collaborate with our architects and engineers to develop innovative high speed analog transceiver solutions for next-generation optical and wireline communication systems. * We are currently hiring for multiple levels for this role. Your level and compensation will be determined by your experience, education, and location. ● Design analog/mixed-signal blocks with a focus on transceivers and broadband circuits interfacing with silicon photonics elements such as trans-impedance amplifiers (TIA) and Tx Driver ● Contribute to the development of complex SoC integration flows, with a strong focus on high-speed circuit design and advanced node integration. You will work closely with photonics and 3DIC packaging teams to co-develop solutions for leading-edge products ● Support micro-architecture development with chip architects by conducting feasibility studies ● Collaborate with members of our design engineering teams (system, digital, analog, photonics) to define electrical requirements ● Drive block-level floorplan, mask design views, and their reviews ● Run post-layout and mixed-signal top-level simulations to validate integration ● Define production and bench-level test plans ● Validate performances of the circuits in the lab ● Mentor junior design engineers
候选人主要从事的工作是高性能计算相关的模拟接口IP的研发，包括不限于D2D/Memory/C2C/板卡互联等。候选人需要完成IP的立项、架构、交付、开发、测试等端到端的工作，需要具备如下能力至少一项（第4项为必备项）： 1.IP立项：可以完成IP 的竞争力分析，确定IP 的长期演进技术方向，并完成IP 架构选型、关键技术分析、竞争力构建策略；主导IP 立项。 2.IP架构：完成IP 架构的建模、指标分解、具体电路的方案调研，并跟踪电路的开发，确保指标达成和竞争力的实现。 3.IP 交付：需要熟悉数模混合IP交付的流程，可以配合封装、测试、模型、算法、数字设计、数字验证完成模拟IP 相关交付件的需求梳理、交付件对齐、数模混合验证等工作。 4.IP 开发：需要至少CMU（时钟管理单元）、TX、RX 一个领域有深入的理解，可以选择适配IP 的最有竞争力的方案；并完成组件的设计、指导CL布局布线、 仿真验证等。 5.IP 测试：完成测试需求的收集、评审；测试用例的完备性分析；测试方案的开发和验证；回片的测试的启动和测试问题的攻关。
The candidate will be the major interface to the optical IO analog/mixed signal design team or vendor. As a member of the analog team, you’ll collaborate with our architects and engineers to develop innovative high speed analog transceiver solutions for next-generation optical and wireline communication systems. * We are currently hiring for multiple levels for this role. Your level and compensation will be determined by your experience, education, and location. ● Design analog/mixed-signal blocks with a focus on transceivers and broadband circuits interfacing with silicon photonics elements such as trans-impedance amplifiers (TIA) and Tx Driver ● Contribute to the development of complex SoC integration flows, with a strong focus on high-speed circuit design and advanced node integration. You will work closely with photonics and 3DIC packaging teams to co-develop solutions for leading-edge products ● Support micro-architecture development with chip architects by conducting feasibility studies ● Collaborate with members of our design engineering teams (system, digital, analog, photonics) to define electrical requirements ● Drive block-level floorplan, mask design views, and their reviews ● Run post-layout and mixed-signal top-level simulations to validate integration ● Define production and bench-level test plans ● Validate performances of the circuits in the lab ● Mentor junior design engineers