理想汽车AI芯片架构师

We are seeking a highly skilled and innovative AI Chip Architect who will play a key role in the development of cutting-edge AI hardware. The ideal candidate is a visionary and a problem-solver, capable of designing complex chip architectures optimized for performance, efficiency, and scalability. In this role, you will work with software and hardware engineering groups to define state-of-the-art AI chip architecture for high-performance computing system in Data Center. Key Responsibilities: * Define the architecture for the next-generation AI chips, including high-performance computing system, hierarchically memory/cache system, and high-speed interconnects. * Collaborate with a cross-functional team of hardware engineers, software developers, and machine learning specialists to ensure designs meet the performance and power requirements of AI applications. * Propose and evaluate architectural innovations to improve throughput, latency, energy efficiency, and scalability of AI processing. * Produce thorough documentation to articulate design decisions and architectural trade-offs to stakeholders. * Participate in design reviews, providing critical feedback and insights to improve chip quality and performance. * Oversee and contribute to the entire lifecycle of the chip design process, from specification to production and post-production support. * Mentor junior engineers and contribute to a culture of technical excellence.

We are seeking a highly skilled and innovative AI Chip Architect who will play a key role in the development of cutting-edge AI hardware. The ideal candidate is a visionary and a problem-solver, capable of designing complex chip architectures optimized for performance, efficiency, and scalability. In this role, you will work with software and hardware engineering groups to define state-of-the-art AI chip architecture for high-performance computing system in Data Center. Key Responsibilities: * Define the architecture for the next-generation AI chips, including high-performance computing system, hierarchically memory/cache system, and high-speed interconnects. * Collaborate with a cross-functional team of hardware engineers, software developers, and machine learning specialists to ensure designs meet the performance and power requirements of AI applications. * Propose and evaluate architectural innovations to improve throughput, latency, energy efficiency, and scalability of AI processing. * Produce thorough documentation to articulate design decisions and architectural trade-offs to stakeholders. * Participate in design reviews, providing critical feedback and insights to improve chip quality and performance. * Oversee and contribute to the entire lifecycle of the chip design process, from specification to production and post-production support. * Mentor junior engineers and contribute to a culture of technical excellence.

1. 负责算力效能转化：深入分析 AI 场景和应用模式，提出最大化释放芯片服务器算力潜能的优化方案。针对 MoE 架构、长上下文等特定大模型场景，设计软硬协同的专属优化策略，将阿里 PPU（真武 810/810E）的理论算力峰值转化为客户可感知的实际业务吞吐（Tokens/s） 2. 负责客户侧技术规划：面向国家电网等大型国企/央企客户，输出算力规划建议。主导客户侧深度技术交流，现场解答关于芯片架构、算子兼容性、软件栈及集群性能瓶颈的关键问题。规划设计最优的芯片服务器硬件配置与集群组网方案。

1.软硬件接口定义与验证：参与自研芯片的指令集和编程模型设计，基于模拟器或FPGA平台完成接口功能验证，确保软硬件交互的正确性与一致性； 2.编译与算子优化：基于MLIR/TVM等编译框架，实现深度学习算子到自研指令集的高效映射；通过算子融合、指令流水线调度、内存访问优化等策略，提升芯片算力利用率与执行效率； 3.性能分析与建模：构建系统级性能分析模型，结合指令级模拟器、周期精确模拟器及FPGA原型验证平台，构建多维度性能画像；定位AI负载在指令发射、访存带宽、多核同步等方面的瓶颈，形成性能归因与架构改进建议； 4.软硬协同设计：参与芯片功能验证与性能评估，从系统架构视角提出微架构改进建议，驱动软硬件接口的迭代优化。