智能互联平头哥-AI芯片架构师-上海

We are seeking a highly skilled and innovative AI Chip Architect who will play a key role in the development of cutting-edge AI hardware. The ideal candidate is a visionary and a problem-solver, capable of designing complex chip architectures optimized for performance, efficiency, and scalability. In this role, you will work with software and hardware engineering groups to define state-of-the-art AI chip architecture for high-performance computing system in Data Center. Key Responsibilities: * Define the architecture for the next-generation AI chips, including high-performance computing system, hierarchically memory/cache system, and high-speed interconnects. * Collaborate with a cross-functional team of hardware engineers, software developers, and machine learning specialists to ensure designs meet the performance and power requirements of AI applications. * Propose and evaluate architectural innovations to improve throughput, latency, energy efficiency, and scalability of AI processing. * Produce thorough documentation to articulate design decisions and architectural trade-offs to stakeholders. * Participate in design reviews, providing critical feedback and insights to improve chip quality and performance. * Oversee and contribute to the entire lifecycle of the chip design process, from specification to production and post-production support. * Mentor junior engineers and contribute to a culture of technical excellence.

In this role, you will work with hardware and software engineering groups to define the next-generation inter-chip network architecture for high-performance AI chip and AI network. * Identifies the challenging problems, and evaluate various architectural solutions for the next-generation of network for AI chip and AI Super Pod. * Gets strong influences on future AI products by advanced architecture design as the excellent interface between software and hardware. * Architecture design of AI chip to chip interconnect subsystem, Scale-up Switch chip, C2C link, and etc. * Documents the high-level architecture specification. * Participation in defining the micro-architecture of key subsystem. * Strong technical leadership to achieve successful delivery of final silicon product. * Works closely with design, software, system, and verification team.

1. 从功耗的维度参与软硬件协同策略和芯片总体架构方案设计 2. 负责芯片功耗场景的分析和定义，完成芯片总体功耗目标的制定，并将总体目标分解至各个子系统 3. 设计SoC低功耗架构,包括供电架构（Voltage domain, Power rail和Power domain）和Power Sequence，从PMIC到IP级的电源网络方案，Thermal方案，DVFS方案，Clock domain，以及不同层次的Clock gating方案等 4. 定义SoC和每个子系统的Power state，唤醒方案，以及相应功耗指标 5. 构建SoC层面的性能和功耗仿真平台和验证模型，负责芯片关键功耗场景的环境搭建、仿真验证、功耗测试及结果分析，指导优化算法和前端RTL设计 6. 根据功耗仿真与测试等结果，与软件和硬件团队合作，优化微架构和软硬件策略，提升芯片能效 7. 了解边缘AI芯片技术和性能/功耗优化技术的最新进展，探索新的性能/功耗方法学

1. 承接产品和市场需求，分解到芯片产品定义规格书，并进行相关系统设计，输出AI计算子系统上层和详细系统架构（包括AI算力和算子支持，片上内存和缓存结构，相关编程生态环境和编译器支持，目标AI网络支持的优化支持和相应数据流等） 2. 负责AI计算子系统以及复杂模块的架构/微架构设计，包括和编译器的联合设计，性能/功耗/面积优化和评估，相关领域的竞品分析，竞争力分析等 3. 负责三方相关IP评估和选型 4. 联合相关团队，构建AI计算子系统性能和功耗仿真和验证模型，支持芯片设计和验证