平头哥平头哥-封装工艺专家/高级专家-上海
任职要求
1. 电子，材料等相关专业，硕士或以上学历
Major in electronics, materials, etc., master's degree or above
2. 5年以上封装的相关工作经验；
More than 5 years of relevant work experience in packaging;
3. 有封装厂、Foundry供应商、材料商工作经验者优先；
Experience in packaging factory, foundry supplier and material supplier is preferred;
4. 熟悉不同封装类型的…工作职责
1. 参与封装方案设计，负责芯片封装方案的DFM落地与竞争力 Participate in the Chip packaging solution design，and responsible for the DFM implementation and competitiveness of chip packaging solutions 2. 负责芯片封装相关NPI阶段生产制造及工程工艺质量保障，工艺失效分析及改进措施制定与落地，完成试产到量产的转移 Responsible for chip packaging related NPI manufacturing and engineering process quality assurance, process failure analysis, process improvement and implementation, and complete the transfer from NPI to SVM and HVM production 3. 负责芯片新材料、新封装技术应用的开发 Responsible for the development of new chip materials and new packaging technology applications 4. 负责定期组织供应商交流，梳理供应商能力，为封装方案设计提供能力支撑 Responsible for regularly organizing supplier exchanges (e.g. QTR), sorting out supplier capabilities, and providing capability support for packaging solution design 5. 通过技术维度支持供应链及采购体系维护有竞争力的供应商合作关系 Support the supply chain and procurement system through the technical dimension to maintain a competitive supplier partnership
•与设计团队及3D Fab合作，确定芯片3D物理架构及其技术落地方式，完成产品结构设计和工艺选择； •与3D Fab 合作，设计和优化 3D 芯片工艺集成流程，确保技术方案满足项目要求和技术规格 •负责3D芯片的Tape out；沟通，评估并协调满足3D Fab，2D Fab等各方的技术需求 •负责3D芯片的技术开发，工程验证和量产导入； •负责3D工艺技术问题的监控解决及3D良率提升，持续改进； •负责3D 芯片新的物理架构和技术实现方案的探索；
芯片产业进入后摩尔时代，芯片封装解决方案面临诸多挑战。封装的尺寸、结构、散热、BOM材料、制造工艺，共同影响芯片的性能、成本、以及应用可靠性。作为封装工程师，你将致力于业界最高端芯片封装解决方案的设计、开发、制造、测试、验证，失效分析以及技术创新。在这里，你可以了解并获得最先进的芯片封装技术知识及能力，并和业界顶尖的工程师一起，共同开发最先进封装技术，并推动其持续发展。 As IC industry enters the more than Moore era, chip packaging solutions are facing many challenges. Package size, package structure, heat dissipation, BOM material, and manufacturing process all affect chip performance, cost, and application reliability. As a packaging engineer, you will be dedicated to the design, development, manufacture, testing, verification, failure analysis, and technological innovation of the industry's highest-end chip packaging solutions. Here, you can understand and acquire the relevant knowledge and skills of the most advanced chip packaging technology, and work with the industry's top engineers to jointly develop the most advanced packaging technology and promote its continuous development. 工作职责RESPONSIBILITIES: 作为可靠性测试验证工程师，负责IC可靠性测试方案的制定与设计，保证芯片可靠性测试验证的顺利开展以支撑芯片及产品的开发及量产应用 Work as a Reliability Test and Verification Engineer, define reliability solution and its corresponding hardware design, to ensure reliability test and verification tasks to support the development and mass production of chips and products. 负责芯片及产品相关的失效分析、可靠性寿命评估，并针对失效分析结果联合上下游团队提出适当的解决方案 Responsible for failure analysis and reliability life assessment to chips and products, and work with up/down-stream teams to propose appropriate solutions based on failure analysis results 构建并不断完善可靠性测试流程、系统，支撑公司产品交付 Build and continuously improve the reliability test process and system to support the company's product delivery 从效率、成本等角度对可靠性测试方法、方案开展持续改进及优化，保证产品测试质量的基础上，不断提升可靠性测试竞争力 Continuous improvement and optimization of reliability test methods and solutions from the perspectives of efficiency and cost, and continuously improve reliability test competitiveness on the basis of ensuring product test quality. 跟踪行业技术趋势，开展可靠性寿命评估模型及方法的研究，应对新工艺制程、新结构、新材料的挑战 Track on the industry trend, perform research on reliability life assessment models and methodology, to addressing challenge on new process, new structure and new material.
1. 熟悉memory外围电路的设计以及仿真验证方法。 2. 熟悉存储阵列电路包括行列译码电路、读写电路、灵敏放大器等电路。 3. 熟悉memory的版图布局，电源走线和顶层规划。 4. 熟悉DRAM工艺，并对封装和测试有一定的了解。 5. 熟悉关键电路优化，通过修改电路和版图来满足PPA需求。 6. 有参与项目开发量产的经验。 7. 好的沟通能力跟对工作的热情。
芯片产业进入后摩尔时代，芯片封装解决方案面临诸多挑战。封装的尺寸、结构、散热、BOM材料、制造工艺，共同影响芯片的性能、成本、以及应用可靠性。作为封装工程师，你将致力于业界最高端芯片封装解决方案的设计、开发、制造、测试、验证，失效分析以及技术创新。在这里，你可以了解并获得最先进的芯片封装技术知识及能力，并和业界顶尖的工程师一起，共同开发最先进封装技术，并推动其持续发展。 As IC industry enters the more than Moore era, chip packaging solutions are facing many challenges. Package size, package structure, heat dissipation, BOM material, and manufacturing process all affect chip performance, cost, and application reliability. As a packaging engineer, you will be dedicated to the design, development, manufacture, testing, verification, failure analysis, and technological innovation of the industry's highest-end chip packaging solutions. Here, you can understand and acquire the relevant knowledge and skills of the most advanced chip packaging technology, and work with the industry's top engineers to jointly develop the most advanced packaging technology and promote its continuous development. 工作职责RESPONSIBILITIES: 作为可靠性测试验证工程师，负责IC可靠性测试方案的制定与设计，保证芯片可靠性测试验证的顺利开展以支撑芯片及产品的开发及量产应用 Work as a Reliability Test and Verification Engineer, define reliability solution and its corresponding hardware design, to ensure reliability test and verification tasks to support the development and mass production of chips and products. 负责芯片及产品相关的失效分析、可靠性寿命评估，并针对失效分析结果联合上下游团队提出适当的解决方案 Responsible for failure analysis and reliability life assessment to chips and products, and work with up/down-stream teams to propose appropriate solutions based on failure analysis results 构建并不断完善可靠性测试流程、系统，支撑公司产品交付 Build and continuously improve the reliability test process and system to support the company's product delivery 从效率、成本等角度对可靠性测试方法、方案开展持续改进及优化，保证产品测试质量的基础上，不断提升可靠性测试竞争力 Continuous improvement and optimization of reliability test methods and solutions from the perspectives of efficiency and cost, and continuously improve reliability test competitiveness on the basis of ensuring product test quality. 跟踪行业技术趋势，开展可靠性寿命评估模型及方法的研究，应对新工艺制程、新结构、新材料的挑战 Track on the industry trend, perform research on reliability life assessment models and methodology, to addressing challenge on new process, new structure and new material.