平头哥平头哥-AI芯片SoC设计技术专家-上海
任职要求
* Minimum of 5 years of experience on complex SOC design for proven silicons. * Strong experience on following domain: CPU, GPU, PCIe, Memory, Network. * Experience on one or more of following domain: AXI 4.0(or higher), NOC, Coherency, Virtualization, Security, RAS, …
工作职责
In this role, you will work with software and hardware engineering groups to define the cutting edge of next-generation AI SOC chips for high-performance computing platform in Data Center. * as a design engineer, strong coding skill of system Verilog or Verilog to implement RTL design, develop SOC domain system/interface IP for various SOCs * familiar with ASIC flow to create complex SOCs with advanced methodologies more efficient, participated 3rd party IP integration * strong problem solving and solution for SOC design and IP integration, timing closure, silicon bring up and issue debug * Documents the high-level architecture specification that defines the chip with various sub-systems for the cutting-edge cloud applications. * Works closely with PD, power, system, and verification team to bring up the subsystem

In this role, you will work with software and hardware engineering groups to define the cutting edge of next-generation AI SOC chips for high-performance computing platform in Data Center. * as a design engineer, strong coding skill of system Verilog or Verilog to implement RTL design, develop SOC domain system/interface IP for various SOCs * familiar with ASIC flow to create complex SOCs with advanced methodologies more efficient, participated 3rd party IP integration * strong problem solving and solution for SOC design and IP integration, timing closure, silicon bring up and issue debug * Documents the high-level architecture specification that defines the chip with various sub-systems for the cutting-edge cloud applications. * Works closely with PD, power, system, and verification team to bring up the subsystem
1. 开发性能模型,进行芯片架构探索、瓶颈分析和性能评估,根据模型仿真结果分析影响系统性能的关键点并给出优化思路; 2. 开发功能模型,使得软件驱动及算法可以提前开发和部署,有效缩短芯片产品开发周期; 3. 完成建模平台的可用性优化; 4. 与芯片架构,芯片设计、芯片验证和软件协同工作,提高模型的速度和精度;