平头哥平头哥-芯片后端设计专家-成都
任职要求
BS or MS of EE, 5+ years of experience with the whole RTL2GDS process
* Understanding the state-of-the-art of processing node, custom lib and optimizations
* State-of-the-art experience with CTS and power grid planning, power integrity is a plus
* Experience with relatively large designs (>10m flops) on advanced process nodes and optimization methodology toward top performance and low power
* Unde…工作职责
As a member of the PD team, you will build the next generation networking SoC in advanced process. You will drive the backend flow through the entire RTL2GDS process including floor planning, P&R, timing, PI, and sign-offs. You will also conduct PPA optimization. You responsibilities include, but not limited to: * Build backend flow on state-of-the-art processing node * Create SPECs for PD sign-off * Work closely with architecture and design team to optimize PPA * Floor planning, design synthesis, equivalence checks, partitioning, IO assignment and IP integration, CTS and power grid, P&R , timing closure, power analysis etc. * Design and timing ECOs and sign-offs
工作职责 1、完成芯片的数字后端物理设计（Netlist to GDS out）并tapeout 2、完成芯片的布局布线 3、负责相关的时序分析、功耗分析、电源完整性分析、信号完整性分析等 4、进行芯片的性能、功耗、面积、ESD等方面的优化 5、负责物理验证工作，包括DRC、LVS、ERC、Latchup等等
As a member of the PD team, you will build the next generation networking SoC in advanced process. You will drive the backend flow through the entire RTL2GDS process including floor planning, P&R, timing, PI, and sign-offs. You will also conduct PPA optimization. You responsibilities include, but not limited to: * Build backend flow on state-of-the-art processing node * Create SPECs for PD sign-off * Work closely with architecture and design team to optimize PPA * Floor planning, design synthesis, equivalence checks, partitioning, IO assignment and IP integration, CTS and power grid, P&R , timing closure, power analysis etc. * Design and timing ECOs and sign-offs
As a member of the PD team, you will build the next generation networking SoC in advanced process. You will drive the backend flow through the entire RTL2GDS process including floor planning, P&R, timing, PI, and sign-offs. You will also conduct PPA optimization. You responsibilities include, but not limited to: * Build backend flow on state-of-the-art processing node * Create SPECs for PD sign-off * Work closely with architecture and design team to optimize PPA * Floor planning, design synthesis, equivalence checks, partitioning, IO assignment and IP integration, CTS and power grid, P&R , timing closure, power analysis etc. * Design and timing ECOs and sign-offs
1. 负责低功耗模块Netlist到GDS的物理设计工作，包含floorplan/powerplan/place/CTS/route 2. 负责模块收敛及signoff工作，包括timing analysis & signoff，SI analysis & fix，formal/Lowpower verification 3. 负责模块的物理验证工作，包含DRC/ANT/LVS/ERC/IR/EM/ESD; 4. 负责大型模块的任务分配和管理，制定模块规范，指导子模块的实现 5. 参与数字后端流程的开发与完善，评估、分析和验证EDA工具/流程/工艺。