平头哥平头哥-芯片后端设计专家-成都
任职要求
BS or MS of EE, 5+ years of experience with the whole RTL2GDS process * Understanding the state-of-the-art of processing node, custom lib and optimizations * State-of-the-art experience with CTS and power grid planning, power integrity is a plus * Experience with relatively large designs (>10m flops) on advanced process nodes and optimization methodology toward top performance and low power * Understanding of DVFS, DFT, DFY, DFM is a plus Some hands on with following tools are needed: * Floor planning and P&R: Cadence Innovus and/or Synopsys ICC2 * Synthesis: Synopsys DC/DCG * Formal Verification : Synopsys Formality and/or Cadence LEC * STA: Primetime-DMSA * PI : Apache Redhawk * Physical Design Verification: Synopsys ICV, Mentor Calibre * Scripting: TCL/Perl is required, Python is a plus
工作职责
As a member of the PD team, you will build the next generation networking SoC in advanced process. You will drive the backend flow through the entire RTL2GDS process including floor planning, P&R, timing, PI, and sign-offs. You will also conduct PPA optimization. You responsibilities include, but not limited to: * Build backend flow on state-of-the-art processing node * Create SPECs for PD sign-off * Work closely with architecture and design team to optimize PPA * Floor planning, design synthesis, equivalence checks, partitioning, IO assignment and IP integration, CTS and power grid, P&R , timing closure, power analysis etc. * Design and timing ECOs and sign-offs
1.了解存储应用，分析行业趋势，同时了解内部业务部门的存储需求，从而开发针对阿里巴巴数据中心应用的高度定制和优化的存储硬件和软件。 2. 编写SoC架构规范，作为工程和执行的参考。 3. 开发详细的微体系结构，包括定义硬件分区以及控制和数据流。 4. 与跨职能团队合作测试和验证自行开发的存储产品，以实现大批量生产。 5. 参与并导引整个SoC开发生命周期，涵盖概念，功能定义，实现，FPGA原型设计和测试，文档，交付和维护。 6. 发表相关技术论文，申请专利并与行业合作伙伴合作以推动存储硬件/软件标准化。 7. 为阿里巴巴自研开发的存储硬件和软件定义路线图
1、负责数字电路从RTL到GDSII的实现：包括布局布线、形式验证、静态时序分析、物理验证、功耗及电源网络分析、可靠性等工作，完成投片； 2、负责PnR flow 的搭建和维护。
As a member of the PD team, you will build the next generation networking SoC in advanced process. You will drive the backend flow through the entire RTL2GDS process including floor planning, P&R, timing, PI, and sign-offs. You will also conduct PPA optimization. You responsibilities include, but not limited to: * Build backend flow on state-of-the-art processing node * Create SPECs for PD sign-off * Work closely with architecture and design team to optimize PPA * Floor planning, design synthesis, equivalence checks, partitioning, IO assignment and IP integration, CTS and power grid, P&R , timing closure, power analysis etc. * Design and timing ECOs and sign-offs
As a member of the PD team, you will build the next generation networking SoC in advanced process. You will drive the backend flow through the entire RTL2GDS process including floor planning, P&R, timing, PI, and sign-offs. You will also conduct PPA optimization. You responsibilities include, but not limited to: * Build backend flow on state-of-the-art processing node * Create SPECs for PD sign-off * Work closely with architecture and design team to optimize PPA * Floor planning, design synthesis, equivalence checks, partitioning, IO assignment and IP integration, CTS and power grid, P&R , timing closure, power analysis etc. * Design and timing ECOs and sign-offs