平头哥平头哥-AI芯片互联设计专家-上海

团队介绍：字节芯片研发团队目前工作主要集中在芯片设计环节，主要围绕字节自身业务展开芯片探索，为字节多项业务的专用场景定制硬件优化，设计多款基于先进半导体工艺的云端复杂芯片，以期提升性能、降低成本。早期若干芯片项目已经进入到量产部署阶段，有多次一版成功的投片经历，所用工艺包含多个主流的先进工艺节点。与基础设施各团队之间工作的整体协同，能更容易和更好地发挥芯片研发的价值。 课题介绍： 研究方向：集成电路设计、计算机体系结构、半导体、存储系统、机器学习系统、计算机网络。 芯片设计 1、负责AI芯片架构/微架构探索与方案设计，包括AI推理/训练系统软硬件协同优化、AI模型与算子特性分析、硬件实现方案制定与性能优化、数据中心ASIC芯片微架构探索、RTL设计与集成、业内先进AI芯片微架构跟踪调研、benchmark总结与搭建、芯片互联网络协议与架构演进； 2、重点投入到AI芯片架构、微架构、AI工具链、Scale up/Scale out/Switch等方向。 芯片物理层设计 1、负责ASIC/CPU芯片的物理层研发，具体包括逻辑综合、可测性设计、后端设计、定制IP设计、封装仿真、硅后研发等环节； 2、重点投入到高级封装、高性能IP设计、高性能设计方法学、物理前沿技术（AI for EDA、DTCO）等方向。 课题挑战： 1、探索AI计算、高速互联、存储、先进封装一体化协同架构； 2、负责创新架构与系统设计； 3、与软硬件团队协同，落地AI训练/推理芯片与数据中心系统。 课题价值： 不断探索芯片前沿架构，支持字节火山引擎、抖音、豆包等业务，持续扩展应用领域，赋能LLM、视频/图片生成、视觉理解等大模型方向。以高性能、高精度、高可用性、低成本为目标，提供端云全场景覆盖、软硬件协同的AI芯片和系统解决方案。

In this role, you will work with hardware and software engineering groups to define the next-generation inter-chip network architecture for high-performance AI chip and AI network. * Identifies the challenging problems, and evaluate various architectural solutions for the next-generation of network for AI chip and AI Super Pod. * Gets strong influences on future AI products by advanced architecture design as the excellent interface between software and hardware. * Leads architecture design of AI chip to chip interconnect subsystem, Scale-up Switch chip, C2C link, and etc. * Documents the high-level architecture specification. * Participation in defining the micro-architecture of key subsystem. * Strong technical leadership to achieve successful delivery of final silicon product. * Works closely with design, software, system, and verification team.

In this role, you will work with hardware and software engineering groups to define the next-generation inter-chip network architecture for high-performance AI chip and AI network. * Identifies the challenging problems, and evaluate various architectural solutions for the next-generation of network for AI chip and AI Super Pod. * Gets strong influences on future AI products by advanced architecture design as the excellent interface between software and hardware. * Architecture design of AI chip to chip interconnect subsystem, Scale-up Switch chip, C2C link, and etc. * Documents the high-level architecture specification. * Participation in defining the micro-architecture of key subsystem. * Strong technical leadership to achieve successful delivery of final silicon product. * Works closely with design, software, system, and verification team.

In this role, you will work with architect, hardware and software engineering groups to provide accurate performance modeling of the next-generation inter-chip network architecture for high-performance AI chip and AI network. * Identifies the challenging problems, and evaluate various architectural solutions for the next-generation of network for AI chip and AI Super Pod. * Gets strong influences on future AI products by advanced architecture and evaluates the new architecture with performance modeling using C, C++, SystemC or other high level description languages. * Provides solid and accurate modeling result and influence the direction of next generation of AI networking. * Focus in the domain of AI chip to chip interconnect subsystem, Scale-up Switch chip, C2C link, and etc. * Participation in defining the micro-architecture of key subsystem. * Works closely with design, software, system, and verification team for the final success of products.