英伟达ASIC TOP Floorplan Intern - 2026
任职要求
• Master‘s Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent work experience. • A deep hardware engineering background with a concentration in VLSI and/or Computer Architecture. • Experience in Verilog, System Verilog or similar HVL. • Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure. • Strong communication and interpersonal skills and ability & desire to work as a great teammate should be displayed in your interview. • Python, Perl and C/C++ programming language experience. • Experience using AI coding assistants like Cursor or Github copilot or Windchill Ways to stand out from the crowd: • Experience in driving development of large-scale ASIC floorplan is a huge plus. • Experience building large projects from the ground up using AI tools. • Good command of spoken English
工作职责
• Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development. • Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities. • Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions. • You will build tools and improve existing infrastructure using AI extensively to optimize chip area and speed of execution.
1. 针对数据中心业务需求，与市场/架构及其他团队合作， 设计和实现业务相匹配的大规模SOC产品。 2. 完成设计流程脚本的开发。 3. 负责SOC TOP集成方案、代码交付、质量检查、Lint、CDC等。
The NVIDIA SOC group is looking for ASIC design/verification/infrastructures and methodologies interns. In this position, you will take part in all stages to design modern complex GPU/Tegra chips with state-of-art feature and flows, you will work directly with different global teams, as Arch/SW, ASIC Design/Verification, SOCD/Clocks/SysASIC, DFT and Physical Design teams. Additionally, you will be involved in defining and creating infrastructures and methodologies that create more efficient and flexible SOCs in future. What you’ll be doing: • Participate in chip top integration and assembly • Engage in design/verification work of system-level units • Optimize composing/verification flow, processes, and methodologies • Develop new tools and flows to improve efficiency and quality
THE ROLE: The focus of this role is to plan, build, and execute the design of new and existing features for AMD’s FCH IP (involving management of system power states, reset, clocking as well as some sub-IP controllers), resulting in no bugs in the final design. It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM architecture, AMBA(AXI/AHB/APB) bus, USB(4.0/3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/eSPI/GPIO), General connectivity IPs (I2C/I3C/UART), Ethernet, JTAG, etc.
芯片产业进入后摩尔时代，芯片封装解决方案面临诸多挑战。封装的尺寸、结构、散热、BOM材料、制造工艺，共同影响芯片的性能、成本、以及应用可靠性。作为封装工程师，你将致力于业界最高端芯片封装解决方案的设计、开发、制造、测试、验证，失效分析以及技术创新。在这里，你可以了解并获得最先进的芯片封装技术知识及能力，并和业界顶尖的工程师一起，共同开发最先进封装技术，并推动其持续发展。 As IC industry enters the more than Moore era, chip packaging solutions are facing many challenges. Package size, package structure, heat dissipation, BOM material, and manufacturing process all affect chip performance, cost, and application reliability. As a packaging engineer, you will be dedicated to the design, development, manufacture, testing, verification, failure analysis, and technological innovation of the industry's highest-end chip packaging solutions. Here, you can understand and acquire the relevant knowledge and skills of the most advanced chip packaging technology, and work with the industry's top engineers to jointly develop the most advanced packaging technology and promote its continuous development. 工作职责RESPONSIBILITIES: 作为可靠性测试验证工程师，负责IC可靠性测试方案的制定与设计，保证芯片可靠性测试验证的顺利开展以支撑芯片及产品的开发及量产应用 Work as a Reliability Test and Verification Engineer, define reliability solution and its corresponding hardware design, to ensure reliability test and verification tasks to support the development and mass production of chips and products. 负责芯片及产品相关的失效分析、可靠性寿命评估，并针对失效分析结果联合上下游团队提出适当的解决方案 Responsible for failure analysis and reliability life assessment to chips and products, and work with up/down-stream teams to propose appropriate solutions based on failure analysis results 构建并不断完善可靠性测试流程、系统，支撑公司产品交付 Build and continuously improve the reliability test process and system to support the company's product delivery 从效率、成本等角度对可靠性测试方法、方案开展持续改进及优化，保证产品测试质量的基础上，不断提升可靠性测试竞争力 Continuous improvement and optimization of reliability test methods and solutions from the perspectives of efficiency and cost, and continuously improve reliability test competitiveness on the basis of ensuring product test quality. 跟踪行业技术趋势，开展可靠性寿命评估模型及方法的研究，应对新工艺制程、新结构、新材料的挑战 Track on the industry trend, perform research on reliability life assessment models and methodology, to addressing challenge on new process, new structure and new material.