英伟达ASIC Top Floorplan Design Engineer

• Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development. • Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities. • Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions. • You will build tools and improve existing infrastructure to optimize chip area and speed of execution.

• Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development. • Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities. • Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions. • You will build tools and improve existing infrastructure using AI extensively to optimize chip area and speed of execution.

The NVIDIA GPU clocks group is looking for an excellent ASIC Verification engineer to join the team. The Team is responsible for crafting all aspects of GPU clocking. The team collaborates with the frontend design team to understand the clocking requirements for the chip. We also understand the physical restrictions being placed on the clocks by the backend teams. The GPU clocks group architects, designs and validates the clocks RTL. The complexity of clocks RTL has increased many fold to support our features that power our product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.   What you’ll be doing:  • Develop test plans, tests and verification infrastructure for verifying high-speed Clocking logic, including many aspects: function, DFT, circuit, power, physical design constraints, and etc. You would need to comprehend the functional, test and timing modes for clocks RTL and verify the modes before RTL delivery.  • You will collaborate with other verification engineers and provide creative solutions to reuse programming sequences across various verification hierarchies.  • Build verification environment using SV/UVM methodology Build reusable bus functional models, monitors, checkers and scoreboards  • Drive coverage driven verification closure  • Work with architects, designers and post-silicon teams.  • Methodology development for above tasks.

• STA for hierarchical design. • Constraints creation and validation, timing budget. • Timing closure for both partition and full chip level. • Special timing closure, such as io, test, clock etc. • Synthesis, Netlist quality check, Formal Verification. • Implement chip partition and floorplan. • Function eco creation. • Develop and enhance entire timing closure flow from frontend (pre-layout) to backend (post-layout). • Flow automation development, Methodology in any of above areas.