英伟达ASIC Top Floorplan Design Engineer
任职要求
• Master’s degree in electrical engineering, Computer Science, or Computer Engineering or equivalent work/learning experience.
• 1+ year related experience in Verilog, System Verilog or similar HVL.
• Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.
• Strong communication and interpersonal skills and ability & desire t…工作职责
• Working with architects, design leads, physical design leads and package leads, you will develop, craft and optimize floorplans during early chip development. • Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities. • Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions. • Build tools and improve existing infrastructure using AI extensively to optimize chip area and speed of execution.
• Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development. • Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities. • Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions. • You will build tools and improve existing infrastructure to optimize chip area and speed of execution.
• Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development. • Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities. • Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions. • You will build tools and improve existing infrastructure using AI extensively to optimize chip area and speed of execution.
1. 针对数据中心业务需求，与市场/架构及其他团队合作， 设计和实现业务相匹配的大规模SOC产品。 2. 完成设计流程脚本的开发。 3. 负责SOC TOP集成方案、代码交付、质量检查、Lint、CDC等。
1. 针对数据中心业务需求，与市场/架构及其他团队合作， 设计和实现业务相匹配的大规模SOC产品。 2. 完成设计流程脚本的开发。 3. 负责SOC TOP集成方案、代码交付、质量检查、Lint、CDC等。