英伟达SOC Design and Verification Intern - 2026
任职要求
• Pursuing a BS/MS degree from EE/CS or related majors from a prestigious university. • Familiarity with verification methodology, tools, and flow • Understanding of front-end ASIC design flow, including RTL design, synthesis, and timing analysis • Outstand…
工作职责
The NVIDIA SOC group is looking for ASIC design/verification/infrastructures and methodologies interns. In this position, you will take part in all stages to design modern complex GPU/Tegra chips with state-of-art feature and flows, you will work directly with different global teams, as Arch/SW, ASIC Design/Verification, SOCD/Clocks/SysASIC, DFT and Physical Design teams. Additionally, you will be involved in defining and creating infrastructures and methodologies that create more efficient and flexible SOCs in future. What you’ll be doing: • Participate in chip top integration and assembly • Engage in design/verification work of system-level units • Optimize composing/verification flow, processes, and methodologies • Develop new tools and flows to improve efficiency and quality
What you do at AMD changes everything At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, Immersive platforms, the data center and AI. Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team. SOC Design and Verification Engineer THE ROLE: It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/GPU architecture, AMBA(AXI/AHB/APB) bus, LPDDR&GDDR&HBM architecture, PCI-E/PCI bus, low power design, virtualization, display, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
An exciting internship opportunity to make an immediate contribution to AMD's next generation of technology innovations awaits you! We have a multifaceted, high-energy work environment filled with a diverse group of employees, and we provide outstanding opportunities for developing your career. During your internship, our programs provide the opportunity to collaborate with AMD leaders, receive one-on-one mentorship, attend amazing networking events, and much more. Being part of AMD means receiving hands-on experience that will give you a competitive edge. Together We Advance your career! JOB DETAILS: THE ROLE: Work with talented colleague cross different sites in different countries, to achieve a goal of tapeout on time after all needed sign-off checks. You will be in key position of handling quality of gds delivered to foundry and AMD will provide you a great platform of learning most advanced silicon technologies and exhibiting your excellent skill and personalities. THE PERSON: Given that you will work with teams abroad, English communication skill is a must and team work is also important for our daily work. As a plus, dedicated and innovative sprit is welcomed. KEY RESPONSIBILITIES: Focus on physical verification like DRC, LVS, Antenna, ESD, Latch-up, PERC checks in projects to ensure allocated work can be done within target timeline, to finally make sure tapeout on time. Have chance to learn all PhyV related knowledge and thus have a clear overview of how a large SOC works and how it pass all required verifications till a successful tapeout. Will have chance to exhibit your innovative ideas of enhancing current work flow or creating new tools/flow to automate daily work to increase efficiency.
In this role, you will work with software and hardware engineering groups to define the next-generation inter-chip network architecture for high-performance computing SOC in Data Center Requirement of the Job * Identifies the challenging problems, and evaluate the various solutions for next-generation data center Computing solutions. * Gets strong influences on the shape of future products by advanced architecture design as the excellent interface between software and hardware * Documents the high-level architecture specification that defines the inter-chip network subsystem for the cutting-edge cloud applications. * Works closely with design, system, and verification team to bring up the subsystem
In this role, you will work with architect, hardware and software engineering groups to provide accurate performance modeling of the next-generation inter-chip network architecture for high-performance AI chip and AI network. * Identifies the challenging problems, and evaluate various architectural solutions for the next-generation of network for AI chip and AI Super Pod. * Gets strong influences on future AI products by advanced architecture and evaluates the new architecture with performance modeling using C, C++, SystemC or other high level description languages. * Provides solid and accurate modeling result and influence the direction of next generation of AI networking. * Focus in the domain of AI chip to chip interconnect subsystem, Scale-up Switch chip, C2C link, and etc. * Participation in defining the micro-architecture of key subsystem. * Works closely with design, software, system, and verification team for the final success of products.