英伟达Senior DFT Methodology - Data Analytics Engineer
任职要求
• BSEE (or equivalent experience) with 7+, MSEE with 5+, or PhD with 3+ years of experience in low-power DFT, Data Visualization, Applied Machine Learning or Database Management. • Understanding of fundamental DFT topics, such as, fault modeling, ATPG and fault simulation. • Experience in advanced fault models and Silicon Data Corruption is a plus. • Experience in application of AI for EDA-related problem-solving is a plus.…
工作职责
• As a senior member in our team, you will work with pre-silicon and post-silicon data analytics - visualization, insights and modeling. • You will work with multi-functional teams, implementing brand-new methodologies for improving our outgoing quality of chips including advanced fault modeling and Silicon Lifecycle Management. • You will work on hard-to-solve problems in the Design For Test space which will involve application of algorithm design, using statistical tools to analyze and interpret complex datasets and explorations using Applied AI methods. • In addition, you will help develop and deploy DFT methodologies for our next generation products while also exploring LLM-based solutions. • You will also help mentor junior engineers on test designs and trade-offs including cost and quality.
• Working with customers, partners, and IP vendors to understand SOC/IP solutions best suited for the target use cases and work with them to select and integrate appropriate IP/SOC solutions. • Work with Architects, Chip Leads, and Customers on SOC/IP design, development, timing closure, power analysis, methodology alignment, and program execution to ensure pre-silicon and post-silicon targets are met. • Integrating, evolving, and optimizing IP blocks across a range of products and use cases for NVIDIA SoCs in AI, driving, 6G, cloud, gaming, and other applications. • Working with teams throughout the company (Architects, RTL, PD, Circuit, SI, Thermal, SW, Platform, Operations, Marketing, etc...) on implementing cross-team solutions to achieve project targets. • Drive cross-team methodologies for external soft IP and PHY integration, Nvidia IP release to partner, RTL development and microarchitecture.
The NVIDIA GPU clocks group is looking for an excellent Senior ASIC Verification engineer to join the team. The Team is responsible for crafting all aspects of GPU clocking. The team collaborates with the frontend design team to understand the clocking requirements for the chip. We also understand the physical restrictions being placed on the clocks by the backend teams. The GPU clocks group architects, designs and validates the clocks RTL. The complexity of clocks RTL has increased many fold to support our features that power our product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. What you’ll be doing: • Develop test plans, tests and verification infrastructure for verifying high-speed Clocking logic, including many aspects: function, DFT, circuit, power, physical design constraints, and etc. You would need to comprehend the functional, test and timing modes for clocks RTL and verify the modes before RTL delivery. • You will collaborate with other verification engineers and provide creative solutions to reuse programming sequences across various verification hierarchies. • Build verification environment using SV/UVM methodology Build reusable bus functional models, monitors, checkers and scoreboards • Drive coverage driven verification closure • Work with architects, designers and post-silicon teams. • Methodology development for above tasks.
