英伟达Synthesis CAD Engineer, Physical Design
任职要求
ASIC-PD synthesis/Logic design implementation team is hiring a senior synthesis flow development engineer. The role needs the candidate to be both expertise on logical and physical design flow (synthesis/PnR) and software development. To maintain and develop synthesis flow at NVIDIA means participating in cutting edge synthesis methodology development and thus contributing to NVIDIA global synthesis users. What You’ll Be Doing: • Responsible for developing/maintaining synthesis methodologies and flow automation. • This includes evaluating and enhancing commercial synthesis tools with vendor and developing internal tools and solutions. • The candidate will also be expected to work as…
工作职责
N/A
THE ROLE: Central DFX (CDFX) is a centralized ASIC design group within AMD’s Technology and Engineering organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. It is also responsible for DFx design methodology and CAD automation tools development to support the global DFX engineering teams across AMD.
THE ROLE: AMD CAD team is part of Central Design Methodology team and be responsible to deliver differentiated ASIC implementation flows (from RTL to GDSII) for all AMD products. You'll be working with the global CAD team on synthesize flows.
负责制造业 AI 数据基座 的工程化建设与落地，实现从数据采集、治理、加工到 AI Ready 数据服务的全链路，支撑领域大模型及其他 AI 应用的落地。 1、数据预处理与质量提升 1.1 设计自动化数据清洗、异常检测、缺失补全、去噪与归一化流程 1.2 开发 多模态数据解析与对齐 工具链（CAD 文件解析、工业图像与工艺文本对齐、传感器信号同步） 1.3 建立持续化数据质量监控与回溯机制，确保训练数据的稳定性与一致性 2、AI 数据加工与标注 2.1 搭建和维护数据标注平台（CVAT、Label Studio 等），并实现批量标注自动化 2.2 开发数据增强、弱监督、半监督等 AI 数据扩充方法，提高数据多样性与泛化能力 2.3 支持合成数据（Synthetic Data）生成与验证 3、特征工程与向量化处理 3.1 开发特征提取、Embedding 生成与向量化存储（Milvus、FAISS、Pinecone 等） 3.2 建设 Feature Store，为大模型训练、RAG（检索增强生成）与实时推理提供高质量特征数据流 4、数据服务化与API开发 4.1 构建标准化数据 API、特征查询接口及实时数据流服务，供算法与应用调用 4.2 优化数据访问性能、扩展性与安全性，支持高并发 AI 场景
- 负责netlist相关的flow搭建（synthesis，formal，LP，PT，PTPX, ECO，etc)。 - 负责全芯片的synthesis regression。 - 负责部分模块的SDC集成和检查。 - 负责复杂模块的PPA优化和检查。 - 负责全芯片的netlist check和sign off。 - 负责分析和解决实现过程中的SDC和前后端时序问题。 - 负责实现流程中的LEC检查和整个ECO流程。 - 负责模块级别的UPF生成与相关检查。