英伟达Synthesis CAD Engineer, Physical Design
任职要求
ASIC-PD synthesis/Logic design implementation team is hiring a senior synthesis flow development engineer. The role needs the candidate to be both expertise on logical and physical design flow (synthesis/PnR) and software development. To maintain and develop synthesis flow at NVIDIA means participating in cutting edge synthesis methodology development and thus contributing to NVIDIA global synthesis users. What You’ll Be Doing: • Responsible for developing/maintaining synthesis methodologies and flow automation. • This includes evaluating and enhancing commercial synthesis tools with vendor and developing internal tools and solutions. • The candidate will also be expected to work as part of our global synthesis supporting team to provide professional suggestions and solutions to our global design teams. What you'll be doing: • BS or MS in Electrical or Computer Engineering or equivalent experience • 3+ years of experience in synthesis and PnR and solid knowledge about logical and physical design implementation. • Power user of commercial tools such as Synopsys FC or Cadence Genus/EDI. • Proficiency experience in TCL, Python, Perl or C++. • Flow development or automation experience in ASIC backend design. • Good communication skills including using English as working language is a must. • Knowledge on power optimization and DFT design is a plus.
工作职责
N/A
- 负责netlist相关的flow搭建（synthesis，formal，LP，PT，PTPX, ECO，etc)。 - 负责全芯片的synthesis regression。 - 负责部分模块的SDC集成和检查。 - 负责复杂模块的PPA优化和检查。 - 负责全芯片的netlist check和sign off。 - 负责分析和解决实现过程中的SDC和前后端时序问题。 - 负责实现流程中的LEC检查和整个ECO流程。 - 负责模块级别的UPF生成与相关检查。
1.完成SOC芯片Synthesis，SDC，STA，Formal，UPF，CLP check等工作，衔接前端设计与DFT/PR工程师 2.负责制定项目signoff标准 3.负责芯片投片前各项signoff（STA/Formal/CLP/Power）检查 4.负责先进工艺的导入，挖掘工艺演进带来的PPA收益
• Chip integration and netlist generation • Synthesis, RTL/netlist quality check, Formal Verification • Constraints creation and validation, timing budget. • Work with ASIC team to analyze/resolve special timing issues. • Cross-Team collaboration to implement chip partitioning and floorplan • Work in conjunction with PR engineers to achieve timing closure • Achieve special mode timing closure, such as io, test, clock, async etc. • Function eco creation and method development • Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout) • Methodology and flow automation development for above areas.
- 负责netlist相关的flow搭建（synthesis，formal，LP，PT，PTPX, ECO，etc)； - 负责全芯片的synthesis regression； - 负责部分模块的SDC集成和检查； - 负责复杂模块的PPA优化和检查； - 负责全芯片的netlist check和sign off； - 负责分析和解决实现过程中的SDC和前后端时序问题； - 负责实现流程中的LEC检查和整个ECO流程； - 负责模块级别的UPF生成与相关检查。