英伟达ASIC TOP Floorplan Design Engineer

工作描述

任职要求
• Master’s degree in electrical engineering, Computer Science, or Computer Engineering and 1+ year equivalent work/learning experience.
• Experience in Verilog, System Verilog or similar HVL.
• Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.
• Strong communication and interpersonal skills and ability & desire to work as a great teammate should be displayed in yo…