英伟达ASIC Engineer - New College Grad 2026
任职要求
• MS degree from EE/CS or related majors from a prestigious university. • Good knowledge in digital circuit design. • Experience in using Verilog HDL. • Experience in various of ASIC EDA tools. • Fluent in English reading and writing. • Self-motivated, good team player. Ways to stand out from the crowd: • Proven ability to work independently as well as in a multi-disciplinary group environment • Good command of C/C++ programming language. • Hand-on experience in any related area is a plus.
工作职责
MMPLEX is NVIDIA's multi-media team. It covers several different directions including Display/Video/Security/Accelerators. Our ASIC role is responsible for RTL design and all other related front-end flow. What you’ll be doing: • Micro architecture design. • RTL (Verilog) coding. • Design implementation using Synopsys/Cadence tools. • Simulate, debug and write tests to verify design functionality and performance. (IP/SOC/FPGA/EMU design/verification direction) • Synthesis/Netlist quality check/Formal verification, Chip partitioning, Timing constraints development for various function/dft modes, Co-work with PR on floorplan and achieve timing closure, Timing sign off. (PD Direction) • Responsible for DFT verification environment setup, own DFT verification and bringup tasks for Clocks, Boundary Scan, Analog and MBIST, Scan, etc. (DFT Direction) • FPGA/EMU synthesis, partitioning and emulating using Synopsys/Cadence etc. Tools and FPGA/EMU ‘s infrastructure flow implementation (FPGA/ EMU direction) • Methodology in any of above areas.
Custom silicon keeps on arising these years. Unlike off-the-shelf silicon produced for general purposes, custom silicon is designed specifically for a particular application or customer. These custom chips are tailored to meet unique performance, power, and feature requirements, allowing for deeper customization of elements like I/O capabilities, memory interfaces, and workload-specific accelerators. NVIDIA custom SOC design team aims to create the best solutions for customers based on NVIDIA Industry-leading technologies. We are looking to grow our team with the smartest people in the world, join us if you want to learn about the world’s leading custom SOC solutions. What you’ll be doing: • Functional and IO IP development • Different IPs integration and release for custom silicon • Build SOC or sub-system, signoff function/performance and QoR • Methodology improvement for high-efficiency custom silicon development
• Study IP/system-level architect to define unitlevel testbench structure. • IP level verification for various features defined for GPU PMU and THERM IP. • Fullchip verification for GPU PMU IP and Tegra THERM IP.
• Chip integration and netlist generation • Synthesis, RTL/netlist quality check, Formal Verification • Constraints creation and validation, timing budget. • Work with ASIC team to analyze/resolve special timing issues. • Cross-Team collaboration to implement chip partitioning and floorplan • Work in conjunction with PR engineers to achieve timing closure • Achieve special mode timing closure, such as io, test, clock, async etc. • Function eco creation and method development • Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout) • Methodology and flow automation development for above areas.
• As a member in our team, you will be responsible for the design and implementation of state-of-the-art designs in test access mechanisms, memory BIST and scan compression. • You'll be responsible for DFT verification environment setup, own DFT verification and bringup tasks for Clocks, Boundary Scan, Analog and MBIST, Scan, etc. You'll have chance to take the lead role for DFT verifications and bringup. • In long term, you can be a DFT lead for verification or extend the expertise to DFT design or implementation.