英伟达DFT Engineer - New College Grad 2026
任职要求
• MS EE or PhD in DFT • Good understanding on ASIC design and verification • Hands on experience on at least one DFT feature: Boundary Scan, 1500, MBIST, Scan, ATPG • Experience in silicon debug and bring-up on the ATE is a plus • Good exposure to clock design, timing/STA, place-n-route or power is a plus • Excellent analytical skills in verification and debug • Strong programming and scripting skills in Perl, Python or Tcl desired • Excellent written and oral communication skills in English with the curiosity to work on challenges
工作职责
• As a member in our team, you will be responsible for the design and implementation of state-of-the-art designs in test access mechanisms, memory BIST and scan compression. • You'll be responsible for DFT verification environment setup, own DFT verification and bringup tasks for Clocks, Boundary Scan, Analog and MBIST, Scan, etc. You'll have chance to take the lead role for DFT verifications and bringup. • In long term, you can be a DFT lead for verification or extend the expertise to DFT design or implementation.
MMPLEX is NVIDIA's multi-media team. It covers several different directions including Display/Video/Security/Accelerators. Our ASIC role is responsible for RTL design and all other related front-end flow. What you’ll be doing: • Micro architecture design. • RTL (Verilog) coding. • Design implementation using Synopsys/Cadence tools. • Simulate, debug and write tests to verify design functionality and performance. (IP/SOC/FPGA/EMU design/verification direction) • Synthesis/Netlist quality check/Formal verification, Chip partitioning, Timing constraints development for various function/dft modes, Co-work with PR on floorplan and achieve timing closure, Timing sign off. (PD Direction) • Responsible for DFT verification environment setup, own DFT verification and bringup tasks for Clocks, Boundary Scan, Analog and MBIST, Scan, etc. (DFT Direction) • FPGA/EMU synthesis, partitioning and emulating using Synopsys/Cadence etc. Tools and FPGA/EMU ‘s infrastructure flow implementation (FPGA/ EMU direction) • Methodology in any of above areas.
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 30 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. We are now looking for Physical Design Engineer in Shanghai & Beijing office. What you’ll be doing: • Analysis on placement, routing, timing, clock, power, noise and DFM and provide optimization strategy • Work on full chip clock distribution • Troubleshoot a wide variety of design and flow complicated issues, and apply proactive intervention. • Collaborate with RTL, DFT and Circuit designers to ensure high quality of design implementation.
THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Develop/Maintain tests for functional verification and performance verification at the SOC level Build testbench components to support the next generation products Maintain or improve current test libraries to support SOC level testing Maintain and improve current hardware simulation environment to speed up the runtime performance and improve the debug facility Verify block/chip level DFX design and features. Develop high coverage and cost effective test patterns. Provide support on Post silicon bring up Provide technical support to other teams
STM (Site Technical Manager) is the single threaded owner for manufacturing technical issues for assigned projects with our Contract Manufacturers, focus on: - Ensure technical readiness for product ramp and serve as manufacturing engineering owner for product PVT and mass production. - Driving manufacture test flow optimization, process and yield improvements to exceed our volume production goals. - Define the manufacture process qualification criteria, manage the qualification activities, and complete the documentation. - Leading our efforts for root cause and corrective action for all manufacturing process related issues, dive deep to analyze the problems found both in and out of the factory. - Participation in design & planning through DFM, Line balancing , as well as Process Yield, Capacity and Cost Modeling. - Work with CM’s engineering teams to identify and escalate manufacturing challenges by enforcing DFM and DFT principles. - Review and approval of Fixtures Designs & Qualification (FATP, Device build) - Review and execute Manufacturing Test Coverage Documents to ensure new products launch. - Work with sustaining engineering team on the opportunities to improve our product, owns the technical readiness of PRQ in CMs. - Periodically audit the CM for manufacture process quality management system.