英伟达Custom SOC ASIC Engineer - New College Grad 2026
任职要求
• Master candidate in EE/CS or related field • Basic C/C++ knowledge is a must • Scripting knowledge (Perl/Python/Shell) • Basic digital circuit/verilog knowledge is a must • Basic verification knowledge is a must Ways to stand out from the crowd: • Q…
工作职责
Custom silicon keeps on arising these years. Unlike off-the-shelf silicon produced for general purposes, custom silicon is designed specifically for a particular application or customer. These custom chips are tailored to meet unique performance, power, and feature requirements, allowing for deeper customization of elements like I/O capabilities, memory interfaces, and workload-specific accelerators. NVIDIA custom SOC design team aims to create the best solutions for customers based on NVIDIA Industry-leading technologies. We are looking to grow our team with the smartest people in the world, join us if you want to learn about the world’s leading custom SOC solutions. What you’ll be doing: • Functional and IO IP development • Different IPs integration and release for custom silicon • Build SOC or sub-system, signoff function/performance and QoR • Methodology improvement for high-efficiency custom silicon development
• Responsible for ASIC design verification for various IPs at IP and SOC levels • Responsible for reference model development and integration • Participate in IP/SOC architecture, micro-architecture reviews, interface with Architecture, SW/FW, Design, and Modeling to work out comprehensive first-time right verification plans • Contribute to the innovative verification methodology development, functional and code coverage closure. • Work on the complex TB creation, direct/random tests and drive the function and coverage to closure. • Contribute to the development of silicon and platform verification strategy and methodology • Triage the fail on SOC level with SOCV/EMU/SW team • Collaborate with IP development teams, and participate in, and support soft and hard IP identification, selection, and IP licensing
• Working with customers, partners, and IP vendors to understand SOC/IP solutions best suited for the target use cases and work with them to select and integrate appropriate IP/SOC solutions. • Work with Architects, Chip Leads, and Customers on SOC/IP design, development, timing closure, power analysis, methodology alignment, and program execution to ensure pre-silicon and post-silicon targets are met. • Integrating, evolving, and optimizing IP blocks across a range of products and use cases for NVIDIA SoCs in AI, driving, 6G, cloud, gaming, and other applications. • Working with teams throughout the company (Architects, RTL, PD, Circuit, SI, Thermal, SW, Platform, Operations, Marketing, etc...) on implementing cross-team solutions to achieve project targets. • Drive cross-team methodologies for external soft IP and PHY integration, Nvidia IP release to partner, RTL development and microarchitecture.
As a member of the PD team, you will build the next generation networking SoC in advanced process. You will drive the backend flow through the entire RTL2GDS process including floor planning, P&R, timing, PI, and sign-offs. You will also conduct PPA optimization. You responsibilities include, but not limited to: * Build backend flow on state-of-the-art processing node * Create SPECs for PD sign-off * Work closely with architecture and design team to optimize PPA * Floor planning, design synthesis, equivalence checks, partitioning, IO assignment and IP integration, CTS and power grid, P&R , timing closure, power analysis etc. * Design and timing ECOs and sign-offs
As a member of the PD team, you will build the next generation networking SoC in advanced process. You will drive the backend flow through the entire RTL2GDS process including floor planning, P&R, timing, PI, and sign-offs. You will also conduct PPA optimization. You responsibilities include, but not limited to: * Build backend flow on state-of-the-art processing node * Create SPECs for PD sign-off * Work closely with architecture and design team to optimize PPA * Floor planning, design synthesis, equivalence checks, partitioning, IO assignment and IP integration, CTS and power grid, P&R , timing closure, power analysis etc. * Design and timing ECOs and sign-offs