英伟达ASIC Physical Design CAD, Timing Constraint and Analysis

任职要求

ASIC-PD team is hiring both junior and senior engineers, whose work scope is physical design from RTL to GSDII: design quality check, synthesis, formal check, partitioning, constraint (for both design and process), async check, timing analysis/fixing/signoff, also all related flow. Join us, you will work together with expertise in all these areas; you will not only work for physical application, but also drive physical friendly design with all related teams: ASIC/P&R/DFT/SI/ARCH etc.; you will work for the most advanced process/technology, the biggest chip in the world.
What You’ll Be Doing
• Develop timing analysis and timing closure methodologies, and implement flow automation for large-scale, high-speed semicustom chips based on deep submicron processes.
• Establish methodologies for timing constraints and SDC (Synopsys Design Constraints) release, including automatic constraint generation, constraint linting, and validation of timing exceptions.
• Take responsibility for EDA tool evaluation,…

工作职责

N/A