英伟达ASIC Design Engineering Intern - 2026

An exciting internship opportunity to make an immediate contribution to AMD's next generation of technology innovations awaits you! We have a multifaceted, high-energy work environment filled with a diverse group of employees, and we provide outstanding opportunities for developing your career. During your internship, our programs provide the opportunity to collaborate with AMD leaders, receive one-on-one mentorship, attend amazing networking events, and much more. Being part of AMD means receiving hands-on experience that will give you a competitive edge. Together We Advance your career! JOB DETAILS: Location: Shanghai Onsite/Hybrid: This role requires the student to work onsite at least 3 days/week throughout internhsip Duration: Jan - Jun 2026 WHAT YOU WILL BE DOING: We are seeking highly motivated Silicon Design Engineer Engineering intern/co-op to join our team. In this role – RTL implementation Collaborate with verification team to achieve good coverage RTL based power, timing and area tracking/analysis

• Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development. • Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities. • Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions. • You will build tools and improve existing infrastructure using AI extensively to optimize chip area and speed of execution.

We are now looking for ASIC Design Interns! NVIDIA MMPLEX team is in Shanghai with more than 300 team members. We deliver cutting-edge IP solutions to multiple NVIDIA product lines, for example: datacenter, GeForce, automotive, networking etc. Our IPs include micro-processor, security, DL/CV accelerators, display, video encoder/decoder, image processor etc. We are looking to grow our teams with the smartest people in the world, join us if you want to learn about world’s leading IP technology and development process.   What you’ll be doing: • Design & verification of hardware Ips • Design & verification methodology study • Work with senior engineers to improve PPA of HW design • Create automation flow to improve engineering efficiency

As an AMD [intern/co-op], you’ll be placed at the epicenter of the AI ecosystem, working alongside experts and industry pioneers. You’ll do important work, learn new skills, expand your network, and gain real-world experience on projects that impact millions of end-users worldwide. Whether you’re an undergrad or a PhD student, your contributions matter—and your experience here will be a launchpad for what comes next. JOB DETAILS: Location: Shanghai Onsite/Hybrid: This role requires the student to work at least 3 days/week Duration: 2026/01 - 2026/06 WHAT YOU WILL BE DOING: We are seeking highly motivated <Role> Engineering intern/co-op to join our team. In this role – 1. Design for Test (DFT) RTL design and coding quality (CDC/LEDA) improvement. 2. Scan insertion, DRC clean, ATPG and pattern simulation 3. Support synthesis owner to fix DFT related netlist issues 4. Work with architect and designer to develop test plan.