英伟达ASIC Intern - 2026
任职要求
• Pursuing Master candidate in EE/CS or related field • Basic C/C++ knowledge is a must • Basic digital circuit/verilog knowledge is a must • Fluent English and good communication skills Ways to stand out from the crowd: • Quick learner, willin…
工作职责
We are now looking for ASIC Design Interns! NVIDIA MMPLEX team is in Shanghai with more than 300 team members. We deliver cutting-edge IP solutions to multiple NVIDIA product lines, for example: datacenter, GeForce, automotive, networking etc. Our IPs include micro-processor, security, DL/CV accelerators, display, video encoder/decoder, image processor etc. We are looking to grow our teams with the smartest people in the world, join us if you want to learn about world’s leading IP technology and development process. What you’ll be doing: • Design & verification of hardware Ips • Design & verification methodology study • Work with senior engineers to improve PPA of HW design • Create automation flow to improve engineering efficiency
• Chip integration and netlist generation, cross-team collaboration to implement chip partitioning and floorplan • Synthesis, RTL/netlist quality check, formal verification, function eco creation • Constraints creation and validation, timing budget, work with ASIC team to analyze/resolve function timing issues, achieve all special timing closure, such as io, test, clock, async etc. • Work in conjunction with PR engineers for chip implementation to achieve full chip timing closue • Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout), flow automation development for above areas • Methodology in any of above areas.
• Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development. • Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities. • Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions. • You will build tools and improve existing infrastructure using AI extensively to optimize chip area and speed of execution.
• Work with IP/system-level architect to define the micro-arch of new features. • Update the existing PMU IP micro-architecture to make it more easily to be leveraged by different chip.
The NVIDIA SOC group is looking for ASIC design/verification/infrastructures and methodologies interns. In this position, you will take part in all stages to design modern complex GPU/Tegra chips with state-of-art feature and flows, you will work directly with different global teams, as Arch/SW, ASIC Design/Verification, SOCD/Clocks/SysASIC, DFT and Physical Design teams. Additionally, you will be involved in defining and creating infrastructures and methodologies that create more efficient and flexible SOCs in future. What you’ll be doing: • Participate in chip top integration and assembly • Engage in design/verification work of system-level units • Optimize composing/verification flow, processes, and methodologies • Develop new tools and flows to improve efficiency and quality