英伟达Senior ASIC Engineer for Simulation, Modeling - Networking Chip Design

N/A

• Responsible for ASIC design verification for various IPs at IP and SOC levels • Responsible for reference model development and integration  • Participate in IP/SOC architecture, micro-architecture reviews, interface with Architecture, SW/FW, Design, and Modeling to work out comprehensive first-time right verification plans • Contribute to the innovative verification methodology development, functional and code coverage closure. • Work on the complex TB creation, direct/random tests and drive the function and coverage to closure. • Contribute to the development of silicon and platform verification strategy and methodology • Triage the fail on SOC level with SOCV/EMU/SW team • Collaborate with IP development teams, and participate in, and support soft and hard IP identification, selection, and IP licensing

The NVIDIA GPU clocks group is looking for an excellent Senior ASIC Verification engineer to join the team. The Team is responsible for crafting all aspects of GPU clocking. The team collaborates with the frontend design team to understand the clocking requirements for the chip. We also understand the physical restrictions being placed on the clocks by the backend teams. The GPU clocks group architects, designs and validates the clocks RTL. The complexity of clocks RTL has increased many fold to support our features that power our product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.   What you’ll be doing:  • Develop test plans, tests and verification infrastructure for verifying high-speed Clocking logic, including many aspects: function, DFT, circuit, power, physical design constraints, and etc. You would need to comprehend the functional, test and timing modes for clocks RTL and verify the modes before RTL delivery.  • You will collaborate with other verification engineers and provide creative solutions to reuse programming sequences across various verification hierarchies.  • Build verification environment using SV/UVM methodology Build reusable bus functional models, monitors, checkers and scoreboards  • Drive coverage driven verification closure  • Work with architects, designers and post-silicon teams.  • Methodology development for above tasks.

The NVIDIA SoC-Clocks team is seeking an Infrastructure and Methodology Engineer dedicated to optimizing chip design, verification, and architectural workflows. This role focuses on developing automation and agentic applications to enhance overall efficiency and quality. The ideal candidate should possess proven full-stack web development and AI application development experience, along with exceptional communication skills. Preference will be given to candidates with a background in fundamental ASIC knowledge. What You’ll Be Doing:  • Acquire comprehensive knowledge of NVIDIA’s design, verification, and architecture development environments, execution procedures, and decision-making methodologies. • Collaborate closely with domain experts (e.g., chip design, verification, and architecture engineers) to identify process bottlenecks and formulate infrastructure improvement solutions. • Design and implement end‑to‑end AI applications, integrating LLM‑based capabilities into web frontends, internal portals, command‑line tools, and other engineering workflows. • Participate in the design and development of the agent application and explore excellent practices in context engineering and harness engineering. Establish rigorous evaluation benchmarks for Agent performance and optimize system to ensure reliability. • Research advanced design and verification tool flows within NVIDIA and the wider industry and develop new applications based on these flows to address emerging challenges.