英伟达Senior ASIC Engineer for Simulation, Modeling - Networking Chip Design
任职要求
• Electrical Engineering B.Sc. or Computer Engineering B.Sc. graduate with high scores or equivalent experience. • 5+ years of experience in uArch modeling. • A team player with good communication and interpersonal skills.
工作职责
• Be an integral part of defining the solution of the next-gen silicon for AI • Work in a simulation/modeling team which verifies core units performance within the Switch silicon. • Micro-architecture of rtl/dynamic verification environments planning for units and modules. • Work closely with multiple teams within organizations such as Architecture, u-arch, and RTL design teams.
The NVIDIA GPU clocks group is looking for an excellent Senior ASIC Verification engineer to join the team. The Team is responsible for crafting all aspects of GPU clocking. The team collaborates with the frontend design team to understand the clocking requirements for the chip. We also understand the physical restrictions being placed on the clocks by the backend teams. The GPU clocks group architects, designs and validates the clocks RTL. The complexity of clocks RTL has increased many fold to support our features that power our product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. What you’ll be doing: • Develop test plans, tests and verification infrastructure for verifying high-speed Clocking logic, including many aspects: function, DFT, circuit, power, physical design constraints, and etc. You would need to comprehend the functional, test and timing modes for clocks RTL and verify the modes before RTL delivery. • You will collaborate with other verification engineers and provide creative solutions to reuse programming sequences across various verification hierarchies. • Build verification environment using SV/UVM methodology Build reusable bus functional models, monitors, checkers and scoreboards • Drive coverage driven verification closure • Work with architects, designers and post-silicon teams. • Methodology development for above tasks.
As chip sizes continue to grow, power efficiency has become paramount across all applications - from data centers to automotive and personal computing. Our PMU IP, developed over the past 13 years, is crucial in optimizing chip performance and efficiency in both idle and active scenarios. The PMU IP consists of a RISC-V core and custom-designed control logic. It collects and processes data from the entire chip, working in tandem with software running on the RISC-V core to determine optimal operating points. We are seeking a Senior Verification Engineer to join our Power Management Unit (PMU) IP team to help building more powerful PMU engine. What you’ll be doing: • Co-work with the IP architect and designer to define the IP verification methodology and test plan. Finishing the IP verification for all new coming features from project to project. • Maintain and improve the SV based unit-level TB to be power powerful and efficient. Maintain the regression and run various of sing-off verification checklists. • Learn and practice formal verification, and use formal tool to assist simulation to raise the verification quality.
• Co-work with the architect to define module architecture/micro-architecture. • Building for NVIDIA next next-generation IPs • Involved in the entire ASIC flow.
• Understand the Switch architecture and data flows • Work in a combined design and verification team specializing in Switch Fullchip works, like assembly, integrations plus a series of QAs to ensure quality • Refine the full Chip working flow to improve the entire team's efficiency • Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW to deliver the FC model for project milestones.