特斯拉Closure Engineer, Closures in White 开闭件工程师，钣金

The Role As a Mechanisms Systems Design Engineer, you will be responsible for conceiving, architecting, designing, and engineering the dynamic exterior systems of Tesla vehicles. You will work alongside pioneering Designers and Engineers through all stages of the product design cycle: From initial sketch and clay modeling, through architecture and design, and finally to validation and product launch. You will be part of the team that creates and executes some of the most notable hallmarks of Tesla design. Responsibilities • Serve as a member of the Vehicle Engineering Team to lead automotive body and closure system development for the Tesla vehicle product lines • Conceptualize, design, engineer and launch structural components and assemblies for system role including power charge door, lighting, and wipers. • Work side by side with side doors, hood and liftgates for CIW (Closures in White) team to integrate and package components within each closure • Achieve innovation-driven closure system targets for appearance, function, quality, cost and weight • Lead investigations which drive the Tesla Design and Styling studio to deliver the optimal balance of form, function and quality • Establish system level architecture and functionality based on market research, design feasibility and prototyping • Work closely with body team to lead master section, sealing flange and hinge axis development • Work directly with Manufacturing Engineering to define optimal processes to achieve world class execution of automotive exterior craftsmanship and fit and finish • Optimize designs with the appropriate analytical and physical assessments • Interpret/develop Tolerance Analysis, DVP&R, CAE, DFM, DFMEA, PFMEA simulations/results and integrate feedback into designs • Manage and collaborate with key suppliers (both internal and external) to support overall vehicle development milestones and prototype/ production build events • Mentor junior designers and provide technique/approach guidance where needed between reviews

Context Works either in Customer Support or in BL Apps (AE, Brion or HMI) and be located in the field working on sustaining, NPI or customer projects. Interfaces with project leaders and mostly within own sector or project team. Applies acquired knowledge to the directly related customer problems and industry solutions, and uses this to tackle problems from multiple angles. For a single competency can contribute to translate customer requirements into existing product capabilities and can demonstrate the value of the product for specific customer situation.

Context Works either in Customer Support or in BL Apps (AE, Brion or HMI) and can be located in the field as well as at HQ working on sustaining, NPI or customer projects. Interfaces with project leaders and mostly within own sector or project team. Applies acquired knowledge to the directly related customer problems and industry solutions, and uses this to tackle problems from multiple angles. For a single competency can contribute to translate customer requirements into existing product capabilities and can demonstrate the value of the product for specific customer situation.

MMPLEX is NVIDIA's multi-media team. It covers several different directions including Display/Video/Security/Accelerators. Our ASIC role is responsible for RTL design and all other related front-end flow.  What you’ll be doing: • Micro architecture design. • RTL (Verilog) coding. • Design implementation using Synopsys/Cadence tools. • Simulate, debug and write tests to verify design functionality and performance. (IP/SOC/FPGA/EMU design/verification direction) • Synthesis/Netlist quality check/Formal verification, Chip partitioning, Timing constraints development for various function/dft modes, Co-work with PR on floorplan and achieve timing closure, Timing sign off.  (PD Direction) • Responsible for DFT verification environment setup, own DFT verification and bringup tasks for Clocks, Boundary Scan, Analog and MBIST, Scan, etc. (DFT Direction) • FPGA/EMU synthesis, partitioning and emulating using Synopsys/Cadence etc. Tools and FPGA/EMU ‘s infrastructure flow implementation (FPGA/ EMU direction) • Methodology in any of above areas.