长鑫存储高速IO 设计总监I High Speed IO Circuit Design Leader(J14611)

任职要求

1.Good known and deep under standing device physics and basic Nano-meter CMOS process; 
  2.At least 7 years of high-speed analog systems experience -- 16Gbps+ designs, High-Frequency N/Frac-N PLLs, Radio Frequency Circuits, etc. is acceptable; 
  3.Experience with analog system modeling and analysis using MATLAB;also,knowledgeable with C/C++,Python and running Debugger; 
  4.Familiar with EDA design tools such as Spectre/hspice,finesim/hsim,Virtuoso,StarRCetc.; 
  5.Strong back ground in Communication The ory,and corresponding DSP concepts and techniques in DFE,FEC,SNR,Frequency/Time; 
  6.Domain analysis(FFT,MatrixAlgebra,Fixed-Point); 
  7.Knowledgeable in high-frequency design methods and measurements--S-parameter,TDR,etc.; 
  8.Back ground in IBIS-AMI(also,prefer some experience with Verilog/RTL); 
  9.Good team player and communication skills; 10.Good learning competency, self-motivated in a flexible and dynamic environment.

工作职责

1.Design/verify/optimize high speed IO circuit blocks used in memory products,DDR4,DDR5,LPDDR4,LPDDR5,GDDR5,GDDR6 etc.; 
 2.Developing advanced(sub-10ps) SerDes—advance PHY architectures, with emphasis on high-speed receivers and signal-conditioning/equalization techniques; 
 3.Modeling and simulations of advance analog systems,algorithm development,as well as mixed-signal system integration,bring-up and debug;
 4.Work with design team,Plan/implement/verifythew hole analog circuit system; 
 5.Design the circuity used for test,main focus on analog block but not limited; 
 6.Guide layout designer floorplan/implement the layout and response post layout simulation; 
 7.Provide support to Product Engineering for silicon test/debug； 
 8.Pre-research the advanced high speed IO technology used in the next generation of DRAM.