理想汽车芯片后端PR设计专家
任职要求
1、本科/硕士学位及以上，微电子/电子/计算机等相关专业毕业，7年以上相关工作经验； 2、熟悉业界主流EDA工具的设计方法学，能够熟练使用；DC/FC/PT/Tempus/Formality/LEC/ICCII/INOVUS 等相关设计工具； 3、熟悉Unix/Linux环境，熟练使用Tcl/Perl/Make/Python脚本编程； 4、参与过大型芯片后端物理实现，熟悉7nm、5nm等先进工艺优先； 5、熟悉后端设计工艺，参与过数字后端库设计、物理验证及芯片TapeOut工作； 6、积极主动，团结合作, 有独立解决问题的能力。
工作职责
1、负责数字电路从RTL到GDSII的实现：包括布局布线、形式验证、静态时序分析、物理验证、功耗及电源网络分析、可靠性等工作，完成投片； 2、负责PnR flow 的搭建和维护。
1、负责数字电路从RTL到GDSII的实现：SoC芯片中的逻辑综合，形式验证，低功耗分析优化和低功耗检查，进行时钟分析、时序约束、STA signoff等工作； 2、负责综合，Formal，低功耗分析和检查，STA等 flow 的搭建和维护； 3、配合设计完成性能功耗面积迭代优化，对接PR团队完成后端设计。
As a member of the PD team, you will build the next generation networking SoC in advanced process. You will drive the backend flow through the entire RTL2GDS process including floor planning, P&R, timing, PI, and sign-offs. You will also conduct PPA optimization. You responsibilities include, but not limited to: * Build backend flow on state-of-the-art processing node * Create SPECs for PD sign-off * Work closely with architecture and design team to optimize PPA * Floor planning, design synthesis, equivalence checks, partitioning, IO assignment and IP integration, CTS and power grid, P&R , timing closure, power analysis etc. * Design and timing ECOs and sign-offs
As a member of the PD team, you will build the next generation networking SoC in advanced process. You will drive the backend flow through the entire RTL2GDS process including floor planning, P&R, timing, PI, and sign-offs. You will also conduct PPA optimization. You responsibilities include, but not limited to: * Build backend flow on state-of-the-art processing node * Create SPECs for PD sign-off * Work closely with architecture and design team to optimize PPA * Floor planning, design synthesis, equivalence checks, partitioning, IO assignment and IP integration, CTS and power grid, P&R , timing closure, power analysis etc. * Design and timing ECOs and sign-offs
As a member of the PD team, you will build the next generation networking SoC in advanced process. You will drive the backend flow through the entire RTL2GDS process including floor planning, P&R, timing, PI, and sign-offs. You will also conduct PPA optimization. You responsibilities include, but not limited to: * Build backend flow on state-of-the-art processing node * Create SPECs for PD sign-off * Work closely with architecture and design team to optimize PPA * Floor planning, design synthesis, equivalence checks, partitioning, IO assignment and IP integration, CTS and power grid, P&R , timing closure, power analysis etc. * Design and timing ECOs and sign-offs