平头哥平头哥-AI chip performance/power architect-上海

We are seeking a highly skilled and innovative AI Chip Architect who will play a key role in the development of cutting-edge AI hardware. The ideal candidate is a visionary and a problem-solver, capable of designing complex chip architectures optimized for performance, efficiency, and scalability. In this role, you will work with software and hardware engineering groups to define state-of-the-art AI chip architecture for high-performance computing system in Data Center. Key Responsibilities: * Define the architecture for the next-generation AI chips, including high-performance computing system, hierarchically memory/cache system, and high-speed interconnects. * Collaborate with a cross-functional team of hardware engineers, software developers, and machine learning specialists to ensure designs meet the performance and power requirements of AI applications. * Propose and evaluate architectural innovations to improve throughput, latency, energy efficiency, and scalability of AI processing. * Produce thorough documentation to articulate design decisions and architectural trade-offs to stakeholders. * Participate in design reviews, providing critical feedback and insights to improve chip quality and performance. * Oversee and contribute to the entire lifecycle of the chip design process, from specification to production and post-production support. * Mentor junior engineers and contribute to a culture of technical excellence.

1. 致力打造世界一流的深度学习硬件计算平台， 跟踪深度学习及系统硬件架构的发展，设计开发高性能低功耗的架构、芯片及硬件产品。 2. 针对阿里巴巴集团业务发展需求，与阿里巴巴的算法和业务团队和作， 规划设计与业务相匹配的异构计算软硬件产品构架。 3. 确保前端设计的质量检查，以及跟后端流程的协做。 1. Build the world-class deep learning platforms. Follow closely with the latest innovations on deep learning algorithms and accelerator architecture. Architect and design deep learning HW acceleration platform for high performance and low power. 2. Target at the specific computation needs of driving business growth. Collaborate with Alibaba algorithm and business teams. Architect and develope heterogenous platforms that drive business growth. 3. Own front-end design quality checks and reviews to present the physical design team with high-quality RTL.

As chip sizes continue to grow, power efficiency has become paramount across all applications - from data centers to automotive and personal computing. Our PMU IP, developed over the past 13 years, is crucial in optimizing chip performance and efficiency in both idle and active scenarios. The PMU IP consists of a RISC-V core and custom-designed control logic. It collects and processes data from the entire chip, working in tandem with software running on the RISC-V core to determine optimal operating points. We are seeking a Senior ASIC Engineer who can help architect the next generation PMU for AI datacenter. What you’ll be doing: • Collaborate with the production SW team and power arch team to define the architecture/micro-architecture for various power features. • Learn how PMU's function impacts the system and support the silicon debug. • Implement the micro-architecture to RTL design.

By submitting your resume, you’re expressing interest in one of our 2026 Hardware ASIC Design Internships. We’ll review resumes on an ongoing basis, and a recruiter may reach out if your experience fits one of our many internship opportunities.   NVIDIA pioneered accelerated computing to tackle challenges no one else can solve. Our work in AI and digital twins is transforming the world's largest industries and profoundly impacting society — from gaming to robotics, self-driving cars to life-saving healthcare, climate change to virtual worlds where we can all connect and create.  Our internships offer an excellent opportunity to expand your career and get hands on experience with one of our industry leading Hardware teams. We’re seeking strategic, ambitious, hard-working, and creative individuals who are passionate about helping us tackle challenges no one else can solve.