平头哥平头哥-芯片互联设计高级专家-上海
任职要求
* Minimum Bachelar degree in Computer Science or Electronics Engineering; M.S. or Ph.D. is preferred
* Minimum of 8 years (for M.S.) 5 years (for Ph.D.) of experience on computer architecture or network chip design with proven silicon result. AI chip, Switch chip, RDMA, RoCE sub-domain is preferred.
* Strong experience in at least one of the following areas is a must:
Server level AI chip design.
Smart NIC/RDMA/RoCE design.
…工作职责
In this role, you will work with software and hardware engineering groups to define the next-generation inter-chip network architecture for high-performance AI chip and AI network. Requirement of the Job * Identifies the challenging problems, and evaluate various solutions for the next-generation of network for AI chip and AI Super Pod. * Gets strong influences on future AI products by advanced architecture design as the excellent interface between software and hardware. * Documents the high-level architecture specification that defines the inter-chip network subsystem for AI chips. * Participation of front-end Implementation of key subsystem. * Strong technical leadership to archive successful delivery of final silicon product. * Works closely with design, system, and verification team.
1、与架构、软件、设计等团队合作构建高端芯片设计验证平台； 2、负责和主导验证方法学和验证策略制定，开发高性能验证架构； 3、负责和主导数据中心芯片互联验证TB开发、环境开发、测试向量开发及调试，覆盖率收集及整体DV signoff的流程开发； 4、负责和主导芯片验证文档的撰写，验证Testbench搭建及实现，Testplan等；
1. 参与模拟IP和各类PHY系统设计工作，包括PCS，总线，流程状态机，测试逻辑，以及模拟控制逻辑的设计。 2. 参与RFID，PLL, DDR,HBM, SERDES等PHY系统设计和debug。 3. 参与设计模拟互联系统，内存系统，和chiplet系统的方案。
候选人主要从事的工作是高性能计算相关的模拟接口IP的研发，包括不限于D2D/Memory/C2C/板卡互联等。候选人需要完成IP的立项、架构、交付、开发、测试等端到端的工作，需要具备如下能力至少一项（第4项为必备项）： 1.IP立项：可以完成IP 的竞争力分析，确定IP 的长期演进技术方向，并完成IP 架构选型、关键技术分析、竞争力构建策略；主导IP 立项。 2.IP架构：完成IP 架构的建模、指标分解、具体电路的方案调研，并跟踪电路的开发，确保指标达成和竞争力的实现。 3.IP 交付：需要熟悉数模混合IP交付的流程，可以配合封装、测试、模型、算法、数字设计、数字验证完成模拟IP 相关交付件的需求梳理、交付件对齐、数模混合验证等工作。 4.IP 开发：需要至少CMU（时钟管理单元）、TX、RX 一个领域有深入的理解，可以选择适配IP 的最有竞争力的方案；并完成组件的设计、指导CL布局布线、 仿真验证等。 5.IP 测试：完成测试需求的收集、评审；测试用例的完备性分析；测试方案的开发和验证；回片的测试的启动和测试问题的攻关。
The candidate will be the major interface to the optical IO analog/mixed signal design team or vendor. As a member of the analog team, you’ll collaborate with our architects and engineers to develop innovative high speed analog transceiver solutions for next-generation optical and wireline communication systems. * We are currently hiring for multiple levels for this role. Your level and compensation will be determined by your experience, education, and location. ● Design analog/mixed-signal blocks with a focus on transceivers and broadband circuits interfacing with silicon photonics elements such as trans-impedance amplifiers (TIA) and Tx Driver ● Contribute to the development of complex SoC integration flows, with a strong focus on high-speed circuit design and advanced node integration. You will work closely with photonics and 3DIC packaging teams to co-develop solutions for leading-edge products ● Support micro-architecture development with chip architects by conducting feasibility studies ● Collaborate with members of our design engineering teams (system, digital, analog, photonics) to define electrical requirements ● Drive block-level floorplan, mask design views, and their reviews ● Run post-layout and mixed-signal top-level simulations to validate integration ● Define production and bench-level test plans ● Validate performances of the circuits in the lab ● Mentor junior design engineers