平头哥平头哥-模拟设计高级/资深专家-上海
任职要求
• Minimum MSEE with 8+ years or Ph.D. with 5+ years of relevant industry experience. • Deep understanding of mixed signal high speed IO/PAD, DDRx PHY, and Serdes PHY design and architectures • Must have hands-on experience of successful design and tape out high quality IO subsystem, PHY, …
工作职责
The candidate will be the major interface to the IO analog/mixed signal design team or vendor. The candidate will be responsible for defining, implementing, and delivering fully functional and production ready chip IO Serdes infrastructure such as PCIE and DDR PHY, Die-to-Die interconnect. Detailed responsibilities include: • All IOs and analog/mixed-signal hard IPs evaluation, selection and integration. • Work with IP design team/IP vender on design review, quality control, schedule management. • Participate in the IO related physical design, provide IO timing constraints for all related interfaces. Drive the mixed-signal IP integration • Participate in the packaging design and focus on Serdes and Die-to-Die interconnect related issues. • Tape-out review sign-offs, including Serdes PHY, DDRx PHY, PLL, Die-to-Die interconnect, Sensors. • In Silicon bring up, coordinate the effort between system team, silicon team and IP vendors in bring up high speed IO interfaces, debug and resolve IP and hard IP issues
The candidate will be the major interface to the optical IO analog/mixed signal design team or vendor. As a member of the analog team, you’ll collaborate with our architects and engineers to develop innovative high speed analog transceiver solutions for next-generation optical and wireline communication systems. * We are currently hiring for multiple levels for this role. Your level and compensation will be determined by your experience, education, and location. ● Design analog/mixed-signal blocks with a focus on transceivers and broadband circuits interfacing with silicon photonics elements such as trans-impedance amplifiers (TIA) and Tx Driver ● Contribute to the development of complex SoC integration flows, with a strong focus on high-speed circuit design and advanced node integration. You will work closely with photonics and 3DIC packaging teams to co-develop solutions for leading-edge products ● Support micro-architecture development with chip architects by conducting feasibility studies ● Collaborate with members of our design engineering teams (system, digital, analog, photonics) to define electrical requirements ● Drive block-level floorplan, mask design views, and their reviews ● Run post-layout and mixed-signal top-level simulations to validate integration ● Define production and bench-level test plans ● Validate performances of the circuits in the lab ● Mentor junior design engineers
The candidate will be the major interface to the IO analog/mixed signal design team or vendor. The candidate will be responsible for defining, implementing, and delivering fully functional and production ready chip IO Serdes infrastructure such as PCIE and DDR PHY, Die-to-Die interconnect. Detailed responsibilities include: • All IOs and analog/mixed-signal hard IPs evaluation, selection and integration. • Work with IP design team/IP vender on design review, quality control, schedule management. • Participate in the IO related physical design, provide IO timing constraints for all related interfaces. Drive the mixed-signal IP integration • Participate in the packaging design and focus on Serdes and Die-to-Die interconnect related issues. • Tape-out review sign-offs, including Serdes PHY, DDRx PHY, PLL, Die-to-Die interconnect, Sensors. • In Silicon bring up, coordinate the effort between system team, silicon team and IP vendors in bring up high speed IO interfaces, debug and resolve IP and hard IP issues
The candidate will be the major interface to the IO analog/mixed signal design team or vendor. The candidate will be responsible for defining, implementing, and delivering fully functional and production ready chip IO Serdes infrastructure such as PCIE and DDR PHY, Die-to-Die interconnect. Detailed responsibilities include: • All IOs and analog/mixed-signal hard IPs evaluation, selection and integration. • Work with IP design team/IP vender on design review, quality control, schedule management. • Participate in the IO related physical design, provide IO timing constraints for all related interfaces. Drive the mixed-signal IP integration • Participate in the packaging design and focus on Serdes and Die-to-Die interconnect related issues. • Tape-out review sign-offs, including Serdes PHY, DDRx PHY, PLL, Die-to-Die interconnect, Sensors. • In Silicon bring up, coordinate the effort between system team, silicon team and IP vendors in bring up high speed IO interfaces, debug and resolve IP and hard IP issues
The candidate will be the major interface to the IO analog/mixed signal design team or vendor. The candidate will be responsible for defining, implementing, and delivering fully functional and production ready chip IO Serdes infrastructure such as PCIE and DDR PHY, Die-to-Die interconnect. Detailed responsibilities include: • All IOs and analog/mixed-signal hard IPs evaluation, selection and integration. • Work with IP design team/IP vender on design review, quality control, schedule management. • Participate in the IO related physical design, provide IO timing constraints for all related interfaces. Drive the mixed-signal IP integration • Participate in the packaging design and focus on Serdes and Die-to-Die interconnect related issues. • Tape-out review sign-offs, including Serdes PHY, DDRx PHY, PLL, Die-to-Die interconnect, Sensors. • In Silicon bring up, coordinate the effort between system team, silicon team and IP vendors in bring up high speed IO interfaces, debug and resolve IP and hard IP issues