英伟达ASIC Physical Design Engineer
任职要求
• MS in EE or Microelectronics is preferred • 2+ years of project experience in IC design implementation • Courses taken in circuit design, digital design • Hand-on experience in EDA software from Synops…
工作职责
• Chip integration and netlist generation • Synthesis • RTL/netlist quality check, Formal Verification, constraints creation and validation, timing budget. • Work with ASIC team to analyze/resolve special timing issues. • Cross-Team collaboration to implement chip partitioning and floorplan • Work in conjunction with PR engineers to achieve timing closure for both partition and full chip level; Achieve special mode timing closure, such as io, test, clock, async etc. • Function eco creation; Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout) • Flow automation development for above areas; Methodology in any of above areas.
• Chip integration and netlist generation • Synthesis, RTL/netlist quality check, Formal Verification • Constraints creation and validation, timing budget. • Work with ASIC team to analyze/resolve special timing issues. • Cross-Team collaboration to implement chip partitioning and floorplan • Work in conjunction with PR engineers to achieve timing closure • Achieve special mode timing closure, such as io, test, clock, async etc. • Function eco creation and method development • Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout) • Methodology and flow automation development for above areas.
• Develop and validate flows for ASIC backend library quality check, maintain and release methodology. • Build and validate flows for design level lib cells usage auditing. • Setup flows/methodology on library in deep submicron physical effects such as aging, self heating, etc.
THE ROLE: We are looking for an adaptive, self-motivative physical design engineer to join our team. As a key contributor, you will be part of a engineering team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Phyiscal Design Engineering team, as part of SoC team, furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.
• Working with architects, design leads, physical design leads and package leads, you will develop, craft and optimize floorplans during early chip development. • Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities. • Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions. • Build tools and improve existing infrastructure using AI extensively to optimize chip area and speed of execution.