英伟达ASIC Physical Design Engineer
任职要求
• MS in EE or Microelectronics is preferred • 2+ years of project experience in IC design implementation • Courses taken in circuit design, digital design • Hand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (RC compiler/LEC) is helpful • Proficient user of Python or TCL is helpful • Proficient in English reading and writing With competitive salaries and a generous benefits package,
工作职责
• Chip integration and netlist generation • Synthesis • RTL/netlist quality check, Formal Verification, constraints creation and validation, timing budget. • Work with ASIC team to analyze/resolve special timing issues. • Cross-Team collaboration to implement chip partitioning and floorplan • Work in conjunction with PR engineers to achieve timing closure for both partition and full chip level; Achieve special mode timing closure, such as io, test, clock, async etc. • Function eco creation; Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout) • Flow automation development for above areas; Methodology in any of above areas.
• Chip integration and netlist generation • Synthesis, RTL/netlist quality check, Formal Verification • Constraints creation and validation, timing budget. • Work with ASIC team to analyze/resolve special timing issues. • Cross-Team collaboration to implement chip partitioning and floorplan • Work in conjunction with PR engineers to achieve timing closure • Achieve special mode timing closure, such as io, test, clock, async etc. • Function eco creation and method development • Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout) • Methodology and flow automation development for above areas.
THE ROLE: We are looking for an adaptive, self-motivative physical design engineer to join our team. As a key contributor, you will be part of a engineering team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Phyiscal Design Engineering team, as part of SoC team, furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.
As a member of the DFP (Design For Power) team you will be responsible for developing and defining low power implementation and EMIR signoff methodology of world class chips under most advanced tech node. Your responsibilities may include, but not be limited to: · Developing physical design flow which including the construction of power delivery network, building of multi-voltage and power gating design, power aware optimization etc. · Defining EMIR signoff methodology at block & chip level, including signoff corner, analysis condition, signoff target and criteria etc. Conducting hotspot/grid weakness study and providing improvement plan · Engaging closely with front-end power team on power estimation and fullchip power budgeting · Working closely with package/PISI team for system level IR convergence for all analog/digital domains and be the 'go-to' person for cross team deliverables · Driving low power design and verification closure by engaging with design/synthesis teams on optimizing chip power structure and power intent to manage physical design risks · Working with EDA vendors to resolve tool issues and drive improvements in design convergence and signoff · Leading full chip EMIR sign-off, monitor EMIR status and manage risks at each milestone to meet tapeout schedule · Driving silicon correlation with a continuous plan to optimize timing/EMIR signoff margin · Empowering physical design engineers to create industry leading chips by providing guidelines on PPA improvement plan from DFP perspective
As a member of the DFP (Design For Power) team you will be responsible for developing and defining low power implementation and EMIR signoff methodology of world class chips under most advanced tech node. Your responsibilities may include, but not be limited to: · Developing physical design flow which including the construction of power delivery network, building of multi-voltage and power gating design, power aware optimization etc. · Defining EMIR signoff methodology at block & chip level, including signoff corner, analysis condition, signoff target and criteria etc. Conducting hotspot/grid weakness study and providing improvement plan · Engaging closely with front-end power team on power estimation and fullchip power budgeting · Working closely with package/PISI team for system level IR convergence for all analog/digital domains and be the 'go-to' person for cross team deliverables · Driving low power design and verification closure by engaging with design/synthesis teams on optimizing chip power structure and power intent to manage physical design risks · Working with EDA vendors to resolve tool issues and drive improvements in design convergence and signoff · Leading full chip EMIR sign-off, monitor EMIR status and manage risks at each milestone to meet tapeout schedule · Driving silicon correlation with a continuous plan to optimize timing/EMIR signoff margin · Empowering physical design engineers to create industry leading chips by providing guidelines on PPA improvement plan from DFP perspective