英伟达ASIC Physical Design Methodology Engineer
任职要求
• MS/PhD in Electrical or Computer Engineering with 2+ years industry experience • Understanding of standard cells/memory/IO/PLL and other hard IP modeling and their usage in the ASIC flow. • Hands-on experience in advanced CMOS technologies, design with FinFET technology 7nm/5nm/3nm and beyond. • Good knowledge with standard cell design & lay…
工作职责
• Develop and validate flows for ASIC backend library quality check, maintain and release methodology. • Build and validate flows for design level lib cells usage auditing. • Setup flows/methodology on library in deep submicron physical effects such as aging, self heating, etc.
• Chip integration and netlist generation • Synthesis, RTL/netlist quality check, Formal Verification • Constraints creation and validation, timing budget. • Work with ASIC team to analyze/resolve special timing issues. • Cross-Team collaboration to implement chip partitioning and floorplan • Work in conjunction with PR engineers to achieve timing closure • Achieve special mode timing closure, such as io, test, clock, async etc. • Function eco creation and method development • Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout) • Methodology and flow automation development for above areas.
• Chip integration and netlist generation • Synthesis • RTL/netlist quality check, Formal Verification, constraints creation and validation, timing budget. • Work with ASIC team to analyze/resolve special timing issues. • Cross-Team collaboration to implement chip partitioning and floorplan • Work in conjunction with PR engineers to achieve timing closure for both partition and full chip level; Achieve special mode timing closure, such as io, test, clock, async etc. • Function eco creation; Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout) • Flow automation development for above areas; Methodology in any of above areas.
THE ROLE: AMD CAD team is part of Design Methodology team and be responsible to deliver differentiated ASIC implementation flows (from RTL to GDSII) for all AMD products. You'll be working with the global CAD team on physical design implementation flows (from netlist to GDSII) and focus on PPA push related areas.
• Chip integration and netlist generation, cross-team collaboration to implement chip partitioning and floorplan • Synthesis, RTL/netlist quality check, formal verification, function eco creation • Constraints creation and validation, timing budget, work with ASIC team to analyze/resolve function timing issues, achieve all special timing closure, such as io, test, clock, async etc. • Work in conjunction with PR engineers for chip implementation to achieve full chip timing closue • Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout), flow automation development for above areas • Methodology in any of above areas.