英伟达ASIC Physical Design Intern - 2026
任职要求
• Currently pursuing a Master's or PhD degree within a relevant or related field • Strong knowledge in IC design • Passionate about technology research and IC backend • Self-driven, good leaning ability, good teamwork • Excellent communication skil…
工作职责
• Chip integration and netlist generation, cross-team collaboration to implement chip partitioning and floorplan • Synthesis, RTL/netlist quality check, formal verification, function eco creation • Constraints creation and validation, timing budget, work with ASIC team to analyze/resolve function timing issues, achieve all special timing closure, such as io, test, clock, async etc. • Work in conjunction with PR engineers for chip implementation to achieve full chip timing closue • Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout), flow automation development for above areas • Methodology in any of above areas.
• Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development. • Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities. • Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions. • You will build tools and improve existing infrastructure using AI extensively to optimize chip area and speed of execution.
The NVIDIA SOC group is looking for ASIC design/verification/infrastructures and methodologies interns. In this position, you will take part in all stages to design modern complex GPU/Tegra chips with state-of-art feature and flows, you will work directly with different global teams, as Arch/SW, ASIC Design/Verification, SOCD/Clocks/SysASIC, DFT and Physical Design teams. Additionally, you will be involved in defining and creating infrastructures and methodologies that create more efficient and flexible SOCs in future. What you’ll be doing: • Participate in chip top integration and assembly • Engage in design/verification work of system-level units • Optimize composing/verification flow, processes, and methodologies • Develop new tools and flows to improve efficiency and quality
• Chip integration and netlist generation • Synthesis, RTL/netlist quality check, Formal Verification • Constraints creation and validation, timing budget. • Work with ASIC team to analyze/resolve special timing issues. • Cross-Team collaboration to implement chip partitioning and floorplan • Work in conjunction with PR engineers to achieve timing closure • Achieve special mode timing closure, such as io, test, clock, async etc. • Function eco creation and method development • Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout) • Methodology and flow automation development for above areas.
• Chip integration and netlist generation • Synthesis • RTL/netlist quality check, Formal Verification, constraints creation and validation, timing budget. • Work with ASIC team to analyze/resolve special timing issues. • Cross-Team collaboration to implement chip partitioning and floorplan • Work in conjunction with PR engineers to achieve timing closure for both partition and full chip level; Achieve special mode timing closure, such as io, test, clock, async etc. • Function eco creation; Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout) • Flow automation development for above areas; Methodology in any of above areas.