英伟达ASIC Engineer Intern, Networking Chip Design - 2026

An exciting internship opportunity to make an immediate contribution to AMD's next generation of technology innovations awaits you! We have a multifaceted, high-energy work environment filled with a diverse group of employees, and we provide outstanding opportunities for developing your career. During your internship, our programs provide the opportunity to collaborate with AMD leaders, receive one-on-one mentorship, attend amazing networking events, and much more. Being part of AMD means receiving hands-on experience that will give you a competitive edge. Together We Advance your career! JOB DETAILS: Location: Shanghai Onsite/Hybrid: This role requires the student to work onsite at least 3 days/week throughout internhsip Duration: Jan - Jun 2026 WHAT YOU WILL BE DOING: We are seeking highly motivated Silicon Design Engineer Engineering intern/co-op to join our team. In this role – RTL implementation Collaborate with verification team to achieve good coverage RTL based power, timing and area tracking/analysis

We are now looking for ASIC Design Interns! NVIDIA MMPLEX team is in Shanghai with more than 300 team members. We deliver cutting-edge IP solutions to multiple NVIDIA product lines, for example: datacenter, GeForce, automotive, networking etc. Our IPs include micro-processor, security, DL/CV accelerators, display, video encoder/decoder, image processor etc. We are looking to grow our teams with the smartest people in the world, join us if you want to learn about world’s leading IP technology and development process.   What you’ll be doing: • Design & verification of hardware Ips • Design & verification methodology study • Work with senior engineers to improve PPA of HW design • Create automation flow to improve engineering efficiency

What you do at AMD changes everything At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, Immersive platforms, the data center and AI. Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team. SOC Design and Verification Engineer THE ROLE: It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/GPU architecture, AMBA(AXI/AHB/APB) bus, LPDDR&GDDR&HBM architecture, PCI-E/PCI bus, low power design, virtualization, display, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.

• Chip integration and netlist generation, cross-team collaboration to implement chip partitioning and floorplan • Synthesis, RTL/netlist quality check, formal verification, function eco creation • Constraints creation and validation, timing budget, work with ASIC team to analyze/resolve function timing issues, achieve all special timing closure, such as io, test, clock, async etc. • Work in conjunction with PR engineers for chip implementation to achieve full chip timing closue • Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout), flow automation development for above areas • Methodology in any of above areas.